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Cleaning up GPIO

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- AW parameter was missing in p2e
- Blocking input data with input enable (alsom done at io pad)
This commit is contained in:
Andreas Olofsson 2016-03-21 11:20:59 -04:00
parent 93154c38f8
commit 7f0491d206
1 changed files with 27 additions and 26 deletions
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53
gpio/hdl/gpio.v
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@ -8,8 +8,8 @@
`include "gpio_regmap.vh" `include "gpio_regmap.vh"
module gpio(/*AUTOARG*/ module gpio(/*AUTOARG*/
// Outputs // Outputs
wait_out, access_out, packet_out, gpio_out, gpio_oen, gpio_irq, wait_out, access_out, packet_out, gpio_out, gpio_oen, gpio_ie,
gpio_data, gpio_irq, gpio_data,
// Inputs // Inputs
nreset, clk, access_in, packet_in, wait_in, gpio_in nreset, clk, access_in, packet_in, wait_in, gpio_in
); );
@ -37,7 +37,8 @@ module gpio(/*AUTOARG*/
//IO signals //IO signals
output [N-1:0] gpio_out; // data to drive to IO pins output [N-1:0] gpio_out; // data to drive to IO pins
output [N-1:0] gpio_oen; // tristate enables for IO pins output [N-1:0] gpio_oen; // output enable (bar)
output [N-1:0] gpio_ie; // input enable
input [N-1:0] gpio_in; // data from IO pins input [N-1:0] gpio_in; // data from IO pins
//global interrupt //global interrupt
@ -82,22 +83,23 @@ module gpio(/*AUTOARG*/
dsync (.dout (gpio_sync[N-1:0]), dsync (.dout (gpio_sync[N-1:0]),
.clk (clk), .clk (clk),
.din (gpio_in[N-1:0])); .din (gpio_in[N-1:0]));
//################################ //################################
//# REGISTER ACCESS DECODE //# REGISTER ACCESS DECODE
//################################ //################################
packet2emesh p2e( packet2emesh #(.AW(AW))
/*AUTOINST*/ p2e(
// Outputs /*AUTOINST*/
.write_in (write_in), // Outputs
.datamode_in (datamode_in[1:0]), .write_in (write_in),
.ctrlmode_in (ctrlmode_in[4:0]), .datamode_in (datamode_in[1:0]),
.dstaddr_in (dstaddr_in[AW-1:0]), .ctrlmode_in (ctrlmode_in[4:0]),
.srcaddr_in (srcaddr_in[AW-1:0]), .dstaddr_in (dstaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]), .srcaddr_in (srcaddr_in[AW-1:0]),
// Inputs .data_in (data_in[AW-1:0]),
.packet_in (packet_in[PW-1:0])); // Inputs
.packet_in (packet_in[PW-1:0]));
assign reg_write = access_in & write_in; assign reg_write = access_in & write_in;
assign reg_read = access_in & ~write_in; assign reg_read = access_in & ~write_in;
@ -113,7 +115,7 @@ module gpio(/*AUTOARG*/
assign outxor_write = reg_write & (dstaddr_in[6:3]==`GPIO_OUTXOR); assign outxor_write = reg_write & (dstaddr_in[6:3]==`GPIO_OUTXOR);
assign imask_write = reg_write & (dstaddr_in[6:3]==`GPIO_IMASK); assign imask_write = reg_write & (dstaddr_in[6:3]==`GPIO_IMASK);
assign out_reg_write = out_write | assign out_reg_write = out_write |
outand_write | outand_write |
outorr_write | outorr_write |
outxor_write; outxor_write;
@ -148,9 +150,11 @@ module gpio(/*AUTOARG*/
out_reg[31:0] <= out_dmux[31:0]; out_reg[31:0] <= out_dmux[31:0];
assign gpio_out[N-1:0] = out_reg[N-1:0]; assign gpio_out[N-1:0] = out_reg[N-1:0];
//################################ //################################
//# INPUT //# INPUT ENABLE
//################################ //################################
//ien //ien
@ -162,12 +166,12 @@ module gpio(/*AUTOARG*/
else if(ien_write) else if(ien_write)
ien_reg[31:0] <= reg_wdata[31:0]; ien_reg[31:0] <= reg_wdata[31:0];
//idata assign gpio_ie[N-1:0] = ien_reg[N-1:0];
always @ (posedge clk)
in_reg[63:0] <= gpio_sync[N-1:0] & ien_reg[63:0];
assign gpio_data[N-1:0] = in_reg[63:0];
//anding here too, just in case IO lib doesn't have input enable
assign gpio_data[N-1:0] = gpio_ie[N-1:0] & gpio_sync[N-1:0];
//################################ //################################
//# EDGE DETECTOR //# EDGE DETECTOR
//################################ //################################
@ -223,9 +227,6 @@ module gpio(/*AUTOARG*/
.read_data (read_data[63:0]), .read_data (read_data[63:0]),
.wait_in (wait_in)); .wait_in (wait_in));
endmodule // gpio endmodule // gpio
// Local Variables: // Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl") // verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")