Changing name back to "oh_mem_dp"

-Now moving to make the names the change, note that since there are many different designs within one SoC/compilation, you will need to have a large if-else somewhere on the design or an automated compiler for each project.
-I saw you have one file asic_mem that contains all the macros in the design with if-else statements inside
-Is there a situation where you would want to decide top what implementtaion you wnt.
-For example, you might want flip-flops sometimes, and other times perhaps a different aspect ratio?
-How to drive the floor-planning, by running experiments, not hard coding!!!
-A designer might want to choose (tall, wide, square, for hard macros)
-Also need to specify hard/soft on a per macro basis

common/hdl/oh_fifo_sync.v

@@ -5,27 +5,42 @@
 //# License:  MIT (see LICENSE file in OH! repository)                        # 
 //#############################################################################
 
-module oh_fifo_sync #(parameter DW        = 104,     //FIFO width
-		      parameter DEPTH     = 32,      //FIFO depth
-		      parameter REG       = 1,       //Register fifo output
-		      parameter PROG_FULL = DEPTH-1, //prog_full threshold  
-		      parameter AW = $clog2(DEPTH),  //rd_count width
-		      parameter DUMPVAR = 1          // dump array
+module oh_fifo_sync 
+  #(parameter DW        = 104,           // FIFO width
+    parameter DEPTH     = 32,            // FIFO depth
+    parameter REG       = 1,             // Register fifo output
+    parameter PROG_FULL = DEPTH-1,       // prog_full threshold  
+    parameter AW        = $clog2(DEPTH), // rd_count width (derived)
+    parameter DUMPVAR   = 1              // dump array (for debug)
     ) 
-(
+   (
+    //basic interface
     input 		clk, // clock
     input 		nreset, //async reset
-   input 	       clear, //clears reset (synchronous signal)
+    input 		clear, //clear fifo (synchronous)
+    input 		shutdown,//power down signal for memory
+    //write port
     input [DW-1:0] 	din, // data to write
     input 		wr_en, // write fifo
-   input 	       rd_en, // read fifo
-   output [DW-1:0]     dout, // output data (next cycle)
     output 		full, // fifo full
     output 		prog_full, // fifo is almost full
+    //read port
+    input 		rd_en, // read fifo    
+    output [DW-1:0] 	dout, // output data (next cycle)
     output 		empty, // fifo is empty  
     output reg [AW-1:0] rd_count // valid entries in fifo
+    //test interface for ASIC (leave floating for non-ASICs)
+    input [7:0] 	memconfig,
+    input [7:0] 	memrepair
+    input 		bist_en,
+    input 		bist_we,
+    input [DW-1:0] 	bist_wem,
+    input [DW-1:0] 	bist_din,
+    input [AW-1:0] 	bist_addr,
+    output [DW-1:0] 	bist_dout,
  );
    
+   //local wires
    reg [AW:0]          wr_addr;
    reg [AW:0]          rd_addr;
    wire 	       fifo_read;
@@ -78,12 +93,12 @@ module oh_fifo_sync #(parameter DW        = 104,     //FIFO width
 		             fifo_empty;
    
    // GENERIC DUAL PORTED MEMORY
-   oh_memory_dp 
+   oh_mem_dp 
      #(.DW(DW),
        .DEPTH(DEPTH),
        .DUMPVAR(DUMPVAR),
        .REG(REG))
-   mem (// read port
+   oh_mem_dp (// read port
 	       .rd_dout	        (dout[DW-1:0]),
 	       .rd_clk		(clk),
 	       .rd_en		(fifo_read),
@@ -94,17 +109,16 @@ module oh_fifo_sync #(parameter DW        = 104,     //FIFO width
   	       .wr_wem		({(DW){1'b1}}),
 	       .wr_addr	        (wr_addr[AW-1:0]),
 	       .wr_din	        (din[DW-1:0]),
-	// not needed
-	.shutdown	(1'b0),
-	.memconfig	(8'b0),
-	.memrepair	(8'b0),
-	.bist_en	(1'b0),
-	.bist_we	(1'b0),
-	.bist_wem	({(DW){1'b0}}),
-	.bist_addr	({(AW){1'b0}}),
-	.bist_din	({(DW){1'b0}})
-	/*AUTOINST*/);
-
+	       // hard macro signals
+	       .shutdown	(shutdown),
+	       .memconfig	(memconfig),
+	       .memrepair	(memrepair),
+	       .bist_en	        (bist_en),
+	       .bist_we	        (bist_we),
+	       .bist_wem	(bist_wem[DW-1:0]),
+	       .bist_addr	(bist_addr[AW-1:0]),
+	       .bist_din	(bist_din[DW-1:0]),
+	       .bist_dout       (bist_dout[DW-1:0]));
 
 `ifdef TARGET_SIM
    assign rd_error = rd_en & empty;

common/hdl/oh_sram_sp.v

@@ -19,22 +19,16 @@ module oh_sram_sp
     input [AW-1:0]  addr, // address
     input [DW-1:0]  din, // data input
     output [DW-1:0] dout, // data output
-    // Power/repair (ASICs)
+    // Power control
     input 	    vss, // common ground   
     input 	    vdd, // periphery power rail
     input 	    vddm, // sram array power rail
     input 	    shutdown, // shutdown signal from always on domain
-    input [MCW-1:0] memconfig, // generic memory config      
-    input [MCW-1:0] memrepair, // repair vector   
-    // BIST interface (ASICs)
-    input 	    bist_en, // bist enable
-    input 	    bist_we, // write enable global signal   
-    input [DW-1:0]  bist_wem, // write enable vector
-    input [AW-1:0]  bist_addr, // address
-    input [DW-1:0]  bist_din  // data input
+    // Repair/macro modes (ASICs)
+    input [7:0]     memconfig, // generic memory config      
+    input [7:0]     memrepair // repair vector   
     );
 
-
 `ifdef CFG_ASIC
    asic_sram_sp #(.DW(DW),
 		  .DEPTH(DEPTH),