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GPIO: Fix pin constraints for FPGA project
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
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@ -16,4 +16,7 @@ set ip_repos [list "."]
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set hdl_files []
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#All constraints files
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set constraints_files []
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set constraints_files [list \
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../../parallella/fpga/parallella_io.xdc \
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../../parallella/fpga/parallella_7020_io.xdc \
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]
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@ -145,6 +145,8 @@ proc create_root_design { parentCell } {
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# Create interface ports
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# Create ports
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set gpio_n [ create_bd_port -dir IO -from 23 -to 0 gpio_n ]
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set gpio_p [ create_bd_port -dir IO -from 23 -to 0 gpio_p ]
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# Create instance: parallella_gpio_0, and set properties
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set parallella_gpio_0 [ create_bd_cell -type ip -vlnv www.parallella.org:user:parallella_gpio:1.0 parallella_gpio_0 ]
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@ -189,6 +191,8 @@ CONFIG.PCW_USE_S_AXI_HP1 {1} ] $processing_system7_0
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connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins parallella_gpio_0/s_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI]
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# Create port connections
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connect_bd_net -net parallella_gpio_0_gpio_n [get_bd_ports gpio_n] [get_bd_pins parallella_gpio_0/gpio_n]
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connect_bd_net -net parallella_gpio_0_gpio_p [get_bd_ports gpio_p] [get_bd_pins parallella_gpio_0/gpio_p]
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connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins processing_system7_0_axi_periph/ARESETN]
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connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins parallella_gpio_0/s_axi_aresetn] [get_bd_pins parallella_gpio_0/sys_nreset] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN]
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connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins parallella_gpio_0/sys_clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/M_AXI_GP1_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK]
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