From 813dd3c17e5383972c119be6012979ab63c015c1 Mon Sep 17 00:00:00 2001
From: Andreas Olofsson <andreas@adapteva.com>
Date: Mon, 28 Mar 2016 09:19:14 -0400
Subject: [PATCH] Adding wrapper for generic pll

---
 src/common/hdl/oh_pll.v | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 src/common/hdl/oh_pll.v

diff --git a/src/common/hdl/oh_pll.v b/src/common/hdl/oh_pll.v
new file mode 100644
index 0000000..a8e311a
--- /dev/null
+++ b/src/common/hdl/oh_pll.v
@@ -0,0 +1,32 @@
+module oh_pll (/*AUTOARG*/
+   // Outputs
+   clkout, locked,
+   // Inputs
+   clkin, nreset, clkfb, pll_en, clkdiv, clkphase, clkmult
+   );
+
+   parameter N = 16;          // number of clock outputs        
+
+   
+   // inputs
+   input            clkin;    // primary clock input
+   input            nreset;   // async active low reset
+   input 	    clkfb;    // feedback clock
+   input 	    pll_en;   // enable pll   
+   input [N*8-1:0]  clkdiv;   // clock divider settings (per clock)
+   input [N*16-1:0] clkphase; // clock phase setting (rise/fall edge)
+   input [7:0] 	    clkmult;  // feedback clock multiplier 	       
+
+   // outputs
+   output [N-1:0]   clkout;   // output clocks
+   output 	    locked;   // PLL locked status
+   
+
+`ifdef TARGET_SIM
+
+   //insert PLL simulation model
+   
+`endif
+   
+   
+endmodule // oh_pll