mirror of
https://github.com/aolofsson/oh.git
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Reorg
This commit is contained in:
Andreas Olofsson
parent
e763cc0250
commit
81b71df54e
@ -1,63 +0,0 @@
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set top_srcdir [file dirname [info script]]/..
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set top_builddir $top_srcdir
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# Alias, some scripts use this atm.
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# TODO: Remove
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set oh_path $top_srcdir
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# TODO: Support building out of tree
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if [info exists ::env(top_builddir)] {
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set top_builddir $::env(top_builddir)
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}
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namespace eval oh {
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namespace eval ip {
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proc create {ip_name ip_dir} {
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# ::create_project $ip_name $ip_dir -force
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::create_project -in_memory
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::update_ip_catalog
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}
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proc add_files {ip_name ip_files} {
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set fileset [::get_filesets sources_1]
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::add_files -fileset $fileset -norecurse -scan_for_includes $ip_files
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::set_property "top" "$ip_name" $fileset
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}
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# TODO: Does not work. filegroup is empty
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proc add_constraints {ip_constr_files {processing_order late}} {
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# set filegroup [::ipx::get_file_groups xilinx_v*synthesis -of_objects [::ipx::current_core]]
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# puts $filegroup
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# set f [::ipx::add_file $ip_constr_files $filegroup]
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# ::set_property -dict \
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# [list \
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# type xdc \
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# library_name {} \
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# processing_order $processing_order \
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# ] \
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# $f
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}
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proc set_properties {ip_dir} {
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set c ::ipx::current_core
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::ipx::package_project -root_dir $ip_dir
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::set_property vendor {www.parallella.org} [$c]
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::set_property library {user} [$c]
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::set_property taxonomy {{/AXI_Infrastructure}} [$c]
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::set_property vendor_display_name {OH!} [$c]
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::set_property company_url {www.parallella.org} [$c]
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::set_property supported_families \
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{
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{virtex7} {Production} \
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{kintex7} {Production} \
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{artix7} {Production} \
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{zynq} {Production} \
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} \
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[$c]
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}
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}; # namespace ip
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}; # namespace oh
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149
memory/dv/fifo_async_model.v
Normal file
149
memory/dv/fifo_async_model.v
Normal file
@ -0,0 +1,149 @@
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/* Parametrized model for xilinx async fifo*/
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module fifo_async_model
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(/*AUTOARG*/
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// Outputs
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full, prog_full, almost_full, dout, empty, valid,
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// Inputs
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wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
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);
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parameter DW = 104; //Fifo width
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parameter DEPTH = 1; //Fifo depth (entries)
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parameter AW = $clog2(DEPTH); //FIFO address width (for model)
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//##########
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//# RESET/CLOCK
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//##########
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input wr_rst; //asynchronous reset
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input rd_rst; //asynchronous reset
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input wr_clk; //write clock
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input rd_clk; //read clock
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//##########
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//# FIFO WRITE
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//##########
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input wr_en;
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input [DW-1:0] din;
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output full;
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output prog_full;
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output almost_full;
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//###########
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//# FIFO READ
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//###########
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input rd_en;
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output [DW-1:0] dout;
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output empty;
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output valid;
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//Wires
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wire [DW/8-1:0] wr_vec;
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wire [AW:0] wr_rd_gray_pointer;
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wire [AW:0] rd_wr_gray_pointer;
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wire [AW:0] wr_gray_pointer;
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wire [AW:0] rd_gray_pointer;
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wire [AW-1:0] rd_addr;
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wire [AW-1:0] wr_addr;
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reg valid;
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assign wr_vec[DW/8-1:0] = {(DW/8){wr_en}};
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//Valid data at output
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always @ (posedge rd_clk or posedge rd_rst)
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if(rd_rst)
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valid <=1'b0;
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else
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valid <= rd_en;
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memory_dp #(.DW(DW),.AW(AW)) memory_dp (
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// Outputs
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.rd_data (dout[DW-1:0]),
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// Inputs
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.wr_clk (wr_clk),
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.wr_en (wr_vec[DW/8-1:0]),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_data (din[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]));
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//Read State Machine
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fifo_empty_block #(.AW(AW)) fifo_empty_block(
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// Outputs
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.rd_fifo_empty (empty),
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.rd_addr (rd_addr[AW-1:0]),
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.rd_gray_pointer(rd_gray_pointer[AW:0]),
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// Inputs
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.reset (rd_rst),
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.rd_clk (rd_clk),
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.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
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.rd_read (rd_en));
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//Write circuit (and full indicator)
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fifo_full_block #(.AW(AW)) full_block (
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// Outputs
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.wr_fifo_almost_full(almost_full),
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.wr_fifo_full (full),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_gray_pointer (wr_gray_pointer[AW:0]),
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// Inputs
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.reset (wr_rst),
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.wr_clk (wr_clk),
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.wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
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.wr_write (wr_en));
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//Half Full Indicator
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fifo_full_block #(.AW(AW-1)) half_full_block (
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// Outputs
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.wr_fifo_almost_full(),
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.wr_fifo_full (prog_full),
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.wr_addr (wr_addr[AW-2:0]),
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.wr_gray_pointer (),
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// Inputs
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.reset (wr_rst),
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.wr_clk (wr_clk),
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.wr_rd_gray_pointer(wr_rd_gray_pointer[AW-1:0]),
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.wr_write (wr_en));
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//Read pointer sync
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synchronizer #(.DW(AW+1)) rd2wr_sync (.out (wr_rd_gray_pointer[AW:0]),
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.in (rd_gray_pointer[AW:0]),
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.reset (wr_rst),
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.clk (wr_clk));
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//Write pointer sync
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synchronizer #(.DW(AW+1)) wr2rd_sync (.out (rd_wr_gray_pointer[AW:0]),
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.in (wr_gray_pointer[AW:0]),
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.reset (rd_rst),
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.clk (rd_clk));
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endmodule // fifo_async
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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@ -1,56 +0,0 @@
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### Find the relative top level path ###
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set top_srcdir [file dirname [info script]]/../../
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set top_builddir $top_srcdir
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# TODO: Support building out of tree
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#if [info exists ::env(top_builddir)] {
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# set top_builddir $::env(top_builddir)
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#}
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namespace eval oh {
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namespace eval ip {
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### CREATE PROJECT ###
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proc create {ip_name ip_dir} {
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# ::create_project $ip_name $ip_dir -force
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::create_project -in_memory
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::update_ip_catalog
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}
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### ADD FILES ###
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proc add_files {ip_name ip_files} {
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set fileset [::get_filesets sources_1]
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::add_files -fileset $fileset -norecurse -scan_for_includes $ip_files
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::set_property "top" "$ip_name" $fileset
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}
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### ADD CONSTRAINTS ###
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proc add_constraints {ip_constr_files {processing_order late}} {
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}
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### IP SETTINGS ###
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proc set_properties {ip_dir} {
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set c ::ipx::current_core
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::ipx::package_project -root_dir $ip_dir
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::set_property vendor {OH!} [$c]
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::set_property library {user} [$c]
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::set_property taxonomy {{/AXI_Infrastructure}} [$c]
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::set_property vendor_display_name {OH!} [$c]
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::set_property company_url {www.parallella.org} [$c]
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::set_property supported_families \
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{
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{virtex7} {Production} \
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{kintex7} {Production} \
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{artix7} {Production} \
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{zynq} {Production} \
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} \
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[$c]
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}
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}; # namespace ip
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}; # namespace oh
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@ -1,36 +0,0 @@
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// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
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// Date : Thu Jul 2 14:31:27 2015
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// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
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// Command : write_verilog -force -mode synth_stub
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// /home/aolofsson/Work_all/oh/elink/scripts/xilinx/temp/temp.srcs/sources_1/ip/fifo_async_104x16/fifo_async_104x16_stub.v
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// Design : fifo_async_104x16
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg484-1
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3.1" *)
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module fifo_async_104x16(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, almost_full, empty, valid, prog_full)
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/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full" */;
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input wr_clk;
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input wr_rst;
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input rd_clk;
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input rd_rst;
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input [103:0]din;
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input wr_en;
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input rd_en;
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output [103:0]dout;
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output full;
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output almost_full;
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output empty;
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output valid;
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output prog_full;
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endmodule
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