From 81b71df54e4ade3fa6645d6c07158dbc30a56345 Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Wed, 4 Nov 2015 19:15:05 -0500 Subject: [PATCH] Reorg --- include/oh.tcl | 63 -------- memory/dv/fifo_async_model.v | 149 ++++++++++++++++++ scripts/xilinx/oh_ip.tcl | 56 ------- .../fifo_async_104x16_stub.v | 36 ----- 4 files changed, 149 insertions(+), 155 deletions(-) delete mode 100644 include/oh.tcl create mode 100644 memory/dv/fifo_async_model.v delete mode 100644 scripts/xilinx/oh_ip.tcl delete mode 100644 xilibs/ip/fifo_async_104x16/fifo_async_104x16_stub.v diff --git a/include/oh.tcl b/include/oh.tcl deleted file mode 100644 index b9afccc..0000000 --- a/include/oh.tcl +++ /dev/null @@ -1,63 +0,0 @@ -set top_srcdir [file dirname [info script]]/.. -set top_builddir $top_srcdir - -# Alias, some scripts use this atm. -# TODO: Remove -set oh_path $top_srcdir - -# TODO: Support building out of tree -if [info exists ::env(top_builddir)] { - set top_builddir $::env(top_builddir) -} - -namespace eval oh { -namespace eval ip { - -proc create {ip_name ip_dir} { -# ::create_project $ip_name $ip_dir -force - ::create_project -in_memory - - ::update_ip_catalog -} - -proc add_files {ip_name ip_files} { - set fileset [::get_filesets sources_1] - ::add_files -fileset $fileset -norecurse -scan_for_includes $ip_files - ::set_property "top" "$ip_name" $fileset -} - -# TODO: Does not work. filegroup is empty -proc add_constraints {ip_constr_files {processing_order late}} { -# set filegroup [::ipx::get_file_groups xilinx_v*synthesis -of_objects [::ipx::current_core]] -# puts $filegroup -# set f [::ipx::add_file $ip_constr_files $filegroup] -# ::set_property -dict \ -# [list \ -# type xdc \ -# library_name {} \ -# processing_order $processing_order \ -# ] \ -# $f -} - -proc set_properties {ip_dir} { - set c ::ipx::current_core - ::ipx::package_project -root_dir $ip_dir - ::set_property vendor {www.parallella.org} [$c] - ::set_property library {user} [$c] - ::set_property taxonomy {{/AXI_Infrastructure}} [$c] - ::set_property vendor_display_name {OH!} [$c] - ::set_property company_url {www.parallella.org} [$c] - - ::set_property supported_families \ - { - {virtex7} {Production} \ - {kintex7} {Production} \ - {artix7} {Production} \ - {zynq} {Production} \ - } \ - [$c] -} - -}; # namespace ip -}; # namespace oh diff --git a/memory/dv/fifo_async_model.v b/memory/dv/fifo_async_model.v new file mode 100644 index 0000000..707beb4 --- /dev/null +++ b/memory/dv/fifo_async_model.v @@ -0,0 +1,149 @@ +/* Parametrized model for xilinx async fifo*/ +module fifo_async_model + (/*AUTOARG*/ + // Outputs + full, prog_full, almost_full, dout, empty, valid, + // Inputs + wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en + ); + + parameter DW = 104; //Fifo width + parameter DEPTH = 1; //Fifo depth (entries) + parameter AW = $clog2(DEPTH); //FIFO address width (for model) + + //########## + //# RESET/CLOCK + //########## + input wr_rst; //asynchronous reset + input rd_rst; //asynchronous reset + input wr_clk; //write clock + input rd_clk; //read clock + + //########## + //# FIFO WRITE + //########## + input wr_en; + input [DW-1:0] din; + output full; + output prog_full; + output almost_full; + + //########### + //# FIFO READ + //########### + input rd_en; + output [DW-1:0] dout; + output empty; + output valid; + + //Wires + wire [DW/8-1:0] wr_vec; + wire [AW:0] wr_rd_gray_pointer; + wire [AW:0] rd_wr_gray_pointer; + wire [AW:0] wr_gray_pointer; + wire [AW:0] rd_gray_pointer; + wire [AW-1:0] rd_addr; + wire [AW-1:0] wr_addr; + + reg valid; + + + assign wr_vec[DW/8-1:0] = {(DW/8){wr_en}}; + + + //Valid data at output + always @ (posedge rd_clk or posedge rd_rst) + if(rd_rst) + valid <=1'b0; + else + valid <= rd_en; + + memory_dp #(.DW(DW),.AW(AW)) memory_dp ( + // Outputs + .rd_data (dout[DW-1:0]), + // Inputs + .wr_clk (wr_clk), + .wr_en (wr_vec[DW/8-1:0]), + .wr_addr (wr_addr[AW-1:0]), + .wr_data (din[DW-1:0]), + .rd_clk (rd_clk), + .rd_en (rd_en), + .rd_addr (rd_addr[AW-1:0])); + + //Read State Machine + fifo_empty_block #(.AW(AW)) fifo_empty_block( + // Outputs + .rd_fifo_empty (empty), + .rd_addr (rd_addr[AW-1:0]), + .rd_gray_pointer(rd_gray_pointer[AW:0]), + // Inputs + .reset (rd_rst), + .rd_clk (rd_clk), + .rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]), + .rd_read (rd_en)); + + //Write circuit (and full indicator) + fifo_full_block #(.AW(AW)) full_block ( + // Outputs + .wr_fifo_almost_full(almost_full), + .wr_fifo_full (full), + .wr_addr (wr_addr[AW-1:0]), + .wr_gray_pointer (wr_gray_pointer[AW:0]), + // Inputs + .reset (wr_rst), + .wr_clk (wr_clk), + .wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]), + .wr_write (wr_en)); + + + //Half Full Indicator + fifo_full_block #(.AW(AW-1)) half_full_block ( + // Outputs + .wr_fifo_almost_full(), + .wr_fifo_full (prog_full), + .wr_addr (wr_addr[AW-2:0]), + .wr_gray_pointer (), + // Inputs + .reset (wr_rst), + .wr_clk (wr_clk), + .wr_rd_gray_pointer(wr_rd_gray_pointer[AW-1:0]), + .wr_write (wr_en)); + + + + //Read pointer sync + synchronizer #(.DW(AW+1)) rd2wr_sync (.out (wr_rd_gray_pointer[AW:0]), + .in (rd_gray_pointer[AW:0]), + .reset (wr_rst), + .clk (wr_clk)); + + //Write pointer sync + synchronizer #(.DW(AW+1)) wr2rd_sync (.out (rd_wr_gray_pointer[AW:0]), + .in (wr_gray_pointer[AW:0]), + .reset (rd_rst), + .clk (rd_clk)); + + +endmodule // fifo_async +// Local Variables: +// verilog-library-directories:("." "../../common/hdl") +// End: + +/* + Copyright (C) 2013 Adapteva, Inc. + Contributed by Andreas Olofsson, Roman Trogan + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program (see the file COPYING). If not, see + . +*/ diff --git a/scripts/xilinx/oh_ip.tcl b/scripts/xilinx/oh_ip.tcl deleted file mode 100644 index 83724ce..0000000 --- a/scripts/xilinx/oh_ip.tcl +++ /dev/null @@ -1,56 +0,0 @@ - -### Find the relative top level path ### -set top_srcdir [file dirname [info script]]/../../ -set top_builddir $top_srcdir - -# TODO: Support building out of tree -#if [info exists ::env(top_builddir)] { -# set top_builddir $::env(top_builddir) -#} - - -namespace eval oh { -namespace eval ip { - -### CREATE PROJECT ### -proc create {ip_name ip_dir} { -# ::create_project $ip_name $ip_dir -force - ::create_project -in_memory - - ::update_ip_catalog -} - -### ADD FILES ### -proc add_files {ip_name ip_files} { - set fileset [::get_filesets sources_1] - ::add_files -fileset $fileset -norecurse -scan_for_includes $ip_files - ::set_property "top" "$ip_name" $fileset -} - -### ADD CONSTRAINTS ### -proc add_constraints {ip_constr_files {processing_order late}} { -} - -### IP SETTINGS ### - -proc set_properties {ip_dir} { - set c ::ipx::current_core - ::ipx::package_project -root_dir $ip_dir - ::set_property vendor {OH!} [$c] - ::set_property library {user} [$c] - ::set_property taxonomy {{/AXI_Infrastructure}} [$c] - ::set_property vendor_display_name {OH!} [$c] - ::set_property company_url {www.parallella.org} [$c] - - ::set_property supported_families \ - { - {virtex7} {Production} \ - {kintex7} {Production} \ - {artix7} {Production} \ - {zynq} {Production} \ - } \ - [$c] -} - -}; # namespace ip -}; # namespace oh diff --git a/xilibs/ip/fifo_async_104x16/fifo_async_104x16_stub.v b/xilibs/ip/fifo_async_104x16/fifo_async_104x16_stub.v deleted file mode 100644 index ee96038..0000000 --- a/xilibs/ip/fifo_async_104x16/fifo_async_104x16_stub.v +++ /dev/null @@ -1,36 +0,0 @@ -// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014 -// Date : Thu Jul 2 14:31:27 2015 -// Host : parallella running 64-bit Ubuntu 14.04.2 LTS -// Command : write_verilog -force -mode synth_stub -// /home/aolofsson/Work_all/oh/elink/scripts/xilinx/temp/temp.srcs/sources_1/ip/fifo_async_104x16/fifo_async_104x16_stub.v -// Design : fifo_async_104x16 -// Purpose : Stub declaration of top-level module interface -// Device : xc7z020clg484-1 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3.1" *) -module fifo_async_104x16(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, almost_full, empty, valid, prog_full) -/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full" */; - input wr_clk; - input wr_rst; - input rd_clk; - input rd_rst; - input [103:0]din; - input wr_en; - input rd_en; - output [103:0]dout; - output full; - - output almost_full; - - output empty; - - output valid; - - output prog_full; -endmodule