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Fixing interface for power gate

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This commit is contained in:
Andreas Olofsson 2016-04-02 22:39:37 -04:00
parent 93e7e5dbab
commit 822bfcbecc
1 changed files with 7 additions and 2 deletions
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9
src/common/hdl/oh_pwr_gate.v
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@ -1,4 +1,9 @@
module oh_pwr_gate (/*AUTOARG*/);
module oh_pwr_gate (/*AUTOARG*/
// Outputs
vddg,
// Inputs
npower, vdd
);
input npower; // active low power on
input vdd; // input supply
@ -8,5 +13,5 @@ module oh_pwr_gate (/*AUTOARG*/);
assign vddg = ((vdd===1'b1) && (npower===1'b0)) ? 1'b1 : 1'bX;
`else
`endif
endmodule // oh_pwr_gate