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Cleanup

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This commit is contained in:
Andreas Olofsson 2015-11-06 14:10:35 -05:00
parent 0a110f6e2c
commit 84b5af5b3a
50 changed files with 36 additions and 8274 deletions
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4
.gitignore vendored
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@ -38,5 +38,7 @@ xgui/
*_stub.vhdl
*.upgrade_log
*_stub.v
*_funcsim.v
*_changelog.txt
src/
*.vhdl

27
parallella/fpga/README.md
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@ -8,3 +8,30 @@ A101040: 7020 + 48 GPIO
parallella_headless.tcl --product number as argument
parallella_display.tcl
parallella_sdr.tcl
---
proc adi_add_bus {bus_name bus_type mode port_maps} {
set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
if { $bus_type == "axis" } {
set abst_type "axis_rtl"
} elseif { $bus_type == "aximm" } {
set abst_type "aximm_rtl"
} else {
set abst_type $bus_type
}
set_property "ABSTRACTION_TYPE_LIBRARY" "interface" $bus
set_property "ABSTRACTION_TYPE_NAME" $abst_type $bus
set_property "ABSTRACTION_TYPE_VENDOR" "xilinx.com" $bus
set_property "ABSTRACTION_TYPE_VERSION" "1.0" $bus
set_property "BUS_TYPE_LIBRARY" "interface" $bus
set_property "BUS_TYPE_NAME" $bus_type $bus
set_property "BUS_TYPE_VENDOR" "xilinx.com" $bus
set_property "BUS_TYPE_VERSION" "1.0" $bus
set_property "CLASS" "bus_interface" $bus
set_property "INTERFACE_MODE" $mode $bus
foreach port_map $port_maps {
adi_add_port_map $bus {*}$port_map
}
}

72
parallella/fpga/headless/system.tcl
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@ -1,72 +0,0 @@
###########################################################
# DEFINITIONS
###########################################################
set design system
set projdir $design
set root "../../.."
set partname "xc7z020clg400-1"
set archive [concat $design.zip]
set report_dir ./reports
set results_dir ./results
#Make this a list (+foreach)
set local_ip_repo ./
###########################################################
# CREATE PROJECT
###########################################################
create_project -force $design $projdir -part $partname
set_property target_language Verilog [current_project]
###########################################################
# Create Report/Results Directory
###########################################################
if ![file exists $report_dir] {file mkdir -p $report_dir}
if ![file exists $results_dir] {file mkdir -p $results_dir}
###########################################################
# Add eLink IP to IP Repository
###########################################################
set ip_repo_paths [get_property ip_repo_paths [current_project]]
set_property ip_repo_paths "$elink_ip_repo_dir $ip_repo_paths" [current_project]
update_ip_catalog
###########################################################
# CREATE BLOCK DESIGN (GUI/TCL COMBO)
###########################################################
create_bd_design "system"
source
validate_bd_design
write_bd_tcl -force $projdir/system_bd.tcl
make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
###########################################################
# ADD FILES
###########################################################
add_files -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
add_files -fileset constrs_1 -norecurse ./${design}_io.xdc
add_files -fileset constrs_1 -norecurse ./${design}_timing.xdc
###########################################################
# Implement Design
###########################################################
launch_runs synth_1
wait_on_run synth_1
launch_runs impl_1
wait_on_run impl_1
###########################################################
# Write Bitstream
###########################################################
launch_runs impl_1 -to_step write_bitstream

75
parallella/fpga/headless/system_init.tcl
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@ -1,75 +0,0 @@
###########################################################
# DEFINITIONS
###########################################################
set design system
set projdir parallella_headless
set root "../../.."
set partname "xc7z020clg400-1"
set archive [concat $design.zip]
set report_dir $projdir/reports
set results_dir $projdir/results
#Make this a list (+foreach)
set local_repos ./
set hdl_files [list \
../../hdl/parallella_headless.v \
]
set constraints_files [list \
./parallella_timing.xdc \
./parallella_io.xdc \
./parallella_7020_io.xdc \
]
###########################################################
# CREATE PROJECT
###########################################################
create_project -force $design $projdir -part $partname
set_property target_language Verilog [current_project]
###########################################################
# Create Report/Results Directory
###########################################################
if ![file exists $report_dir] {file mkdir $report_dir}
if ![file exists $results_dir] {file mkdir $results_dir}
###########################################################
# Add eLink IP to IP Repository
###########################################################
set other_repos [get_property ip_repo_paths [current_project]]
set_property ip_repo_paths "$local_repos $other_repos" [current_project]
update_ip_catalog
###########################################################
# CREATE BLOCK DESIGN (GUI/TCL COMBO)
###########################################################
create_bd_design "system"
source $projdir/system_bd.tcl
make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
###########################################################
# ADD FILES
###########################################################
#HDL
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper
add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
#CONSTRAINTS
if {[string equal [get_filesets -quiet constraints_1] ""]} {
create_fileset -constrset constraints_1
}
if {[llength $constraints_files] != 0} {
add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
}

29
parallella/fpga/headless/system_run.tcl
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@ -1,29 +0,0 @@
###########################################################
# SAVE GUI CHANGES
###########################################################
write_bd_tcl -force ./system_bd.tcl
make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top
###########################################################
# ADD FILES
###########################################################
add_files -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v
add_files -fileset constrs_1 -norecurse ./${design}_io.xdc
add_files -fileset constrs_1 -norecurse ./${design}_timing.xdc
###########################################################
# Implement Design
###########################################################
launch_runs synth_1
wait_on_run synth_1
launch_runs impl_1
wait_on_run impl_1
###########################################################
# Write Bitstream
###########################################################
launch_runs impl_1 -to_step write_bitstream

2
parallella/fpga/parallella_base/build.sh
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@ -1,2 +1,2 @@
#!/bin/bash
vivado -mode batch -source parallella_base_ip.tcl
vivado -mode batch -source run.tcl

46
parallella/fpga/parallella_base/parallella_base/src/arbiter_priority.v
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@ -1,46 +0,0 @@
/* Simple combinatorial priority arbiter
* (lowest position has highest priority)
*
*/
module arbiter_priority(/*AUTOARG*/
// Outputs
grant, await,
// Inputs
request
);
parameter ARW=99;
input [ARW-1:0] request; //request vector
output [ARW-1:0] grant; //grant (one hot)
output [ARW-1:0] await; //grant mask
genvar j;
assign await[0] = 1'b0;
generate for (j=ARW-1; j>=1; j=j-1) begin : gen_arbiter
assign await[j] = |request[j-1:0];
end
endgenerate
//grant circuit
assign grant[ARW-1:0] = request[ARW-1:0] & ~await[ARW-1:0];
endmodule // arbiter_priority
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

414
parallella/fpga/parallella_base/parallella_base/src/axi_elink.v
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@ -1,414 +0,0 @@
module axi_elink(/*AUTOARG*/
// Outputs
timeout, elink_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, chipid, chip_resetb, cclk_p, cclk_n,
mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr,
m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock,
m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid,
m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready,
m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready,
s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata,
s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
// Inputs
reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, m_axi_aresetn, m_axi_awready,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_arready,
m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
s_axi_wstrb, s_axi_wvalid
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
/****************************/
/*CLK AND RESET */
/****************************/
input reset; // active high async reset
input sys_clk; // system clock for AXI
output elink_active; // link is active and ready
/********************************/
/*ELINK I/O PINS */
/********************************/
//Receiver
input rxi_lclk_p, rxi_lclk_n; //link rx clock input
input rxi_frame_p, rxi_frame_n; //link rx frame signal
input [7:0] rxi_data_p, rxi_data_n; //link rx data
output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
//Transmitter
output txo_lclk_p, txo_lclk_n; //link tx clock output
output txo_frame_p, txo_frame_n; //link tx frame signal
output [7:0] txo_data_p, txo_data_n; //link tx data
input txi_wr_wait_p,txi_wr_wait_n; //link tx write pushback input
input txi_rd_wait_p,txi_rd_wait_n; //link tx read pushback input
/********************************/
/*EPIPHANY INTERFACE (I/O PINS) */
/********************************/
output [11:0] chipid; //chip id strap pins for Epiphany
output chip_resetb; //chip reset for Epiphany (active low)
output cclk_p,cclk_n; //high speed clock (up to 1GHz) to Epiphany
/*****************************/
/*MAILBOX (interrupts) */
/*****************************/
output mailbox_not_empty;
output mailbox_full;
//########################
//AXI MASTER INTERFACE
//########################
input m_axi_aresetn; // global reset singal.
//Write address channel
output [M_IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
output [1 : 0] m_axi_awburst; // burst type.
output [1 : 0] m_axi_awlock; // lock type
output [3 : 0] m_axi_awcache; // memory type.
output [2 : 0] m_axi_awprot; // protection type.
output [3 : 0] m_axi_awqos; // quality of service
output m_axi_awvalid; // write address valid
input m_axi_awready; // write address ready
//Write data channel
output [M_IDW-1:0] m_axi_wid;
output [63 : 0] m_axi_wdata; // master interface write data.
output [7 : 0] m_axi_wstrb; // byte write strobes
output m_axi_wlast; // last transfer in a write burst.
output m_axi_wvalid; // indicates data is ready to go
input m_axi_wready; // slave is ready for data
//Write response channel
input [M_IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [M_IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
output [1 : 0] m_axi_arburst; // burst type
output [1 : 0] m_axi_arlock; // lock type
output [3 : 0] m_axi_arcache; // memory type
output [2 : 0] m_axi_arprot; // protection type
output [3 : 0] m_axi_arqos; // --
output m_axi_arvalid; // read address and control is valid
input m_axi_arready; // slave is ready to accept an address
//Read data channel
input [M_IDW-1:0] m_axi_rid;
input [63 : 0] m_axi_rdata; // master read data
input [1 : 0] m_axi_rresp; // status of the read transfer
input m_axi_rlast; // signals last transfer in a read burst
input m_axi_rvalid; // signaling the required read data
output m_axi_rready; // master can accept the readback data
/*****************************/
/*AXI slave interface */
/*****************************/
//Clock and reset
input s_axi_aresetn;
//Read address channel
input [S_IDW-1:0] s_axi_arid; //write address ID
input [31:0] s_axi_araddr;
input [1:0] s_axi_arburst;
input [3:0] s_axi_arcache;
input [1:0] s_axi_arlock;
input [7:0] s_axi_arlen;
input [2:0] s_axi_arprot;
input [3:0] s_axi_arqos;
output s_axi_arready;
input [2:0] s_axi_arsize;
input s_axi_arvalid;
//Write address channel
input [S_IDW-1:0] s_axi_awid; //write address ID
input [31:0] s_axi_awaddr;
input [1:0] s_axi_awburst;
input [3:0] s_axi_awcache;
input [1:0] s_axi_awlock;
input [7:0] s_axi_awlen;
input [2:0] s_axi_awprot;
input [3:0] s_axi_awqos;
input [2:0] s_axi_awsize;
input s_axi_awvalid;
output s_axi_awready;
//Buffered write response channel
output [S_IDW-1:0] s_axi_bid; //write address ID
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
//Read channel
output [S_IDW-1:0] s_axi_rid; //write address ID
output [31:0] s_axi_rdata;
output s_axi_rlast;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
//Write channel
input [S_IDW-1:0] s_axi_wid; //write address ID
input [31:0] s_axi_wdata;
input s_axi_wlast;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
/*#############################################*/
/* END OF BLOCK INTERFACE */
/*#############################################*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output timeout; // From elink of elink.v
// End of automatics
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire rxrd_access; // From elink of elink.v
wire [PW-1:0] rxrd_packet; // From elink of elink.v
wire rxrd_wait; // From emaxi of emaxi.v
wire rxrr_access; // From elink of elink.v
wire [PW-1:0] rxrr_packet; // From elink of elink.v
wire rxrr_wait; // From esaxi of esaxi.v
wire rxwr_access; // From elink of elink.v
wire [PW-1:0] rxwr_packet; // From elink of elink.v
wire rxwr_wait; // From emaxi of emaxi.v
wire txrd_access; // From esaxi of esaxi.v
wire [PW-1:0] txrd_packet; // From esaxi of esaxi.v
wire txrd_wait; // From elink of elink.v
wire txrr_access; // From emaxi of emaxi.v
wire [PW-1:0] txrr_packet; // From emaxi of emaxi.v
wire txrr_wait; // From elink of elink.v
wire txwr_access; // From esaxi of esaxi.v
wire [PW-1:0] txwr_packet; // From esaxi of esaxi.v
wire txwr_wait; // From elink of elink.v
// End of automatics
//########################################################
//ELINK
//########################################################
defparam elink.IOSTD_ELINK = IOSTD_ELINK;
defparam elink.ETYPE = ETYPE;
elink elink(.sys_reset (reset), //por reset needed for elink_en
/*AUTOINST*/
// Outputs
.elink_active (elink_active),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.chipid (chipid[11:0]),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.chip_resetb (chip_resetb),
.mailbox_not_empty (mailbox_not_empty),
.mailbox_full (mailbox_full),
.timeout (timeout),
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.txrr_wait (txrr_wait),
// Inputs
.sys_clk (sys_clk),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]));
//########################################################
//AXI SLAVE
//########################################################
defparam esaxi.S_IDW=S_IDW;
esaxi esaxi (.s_axi_aclk (sys_clk),
/*AUTOINST*/
// Outputs
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.rxrr_wait (rxrr_wait),
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock[1:0]),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock[1:0]),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
//########################################################
//AXI MASTER INTERFACE
//########################################################
defparam emaxi.M_IDW=M_IDW;
emaxi emaxi (.m_axi_aclk (sys_clk),
/*AUTOINST*/
// Outputs
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock[1:0]),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock[1:0]),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
// Inputs
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.txrr_wait (txrr_wait),
.m_axi_aresetn (m_axi_aresetn),
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
.m_axi_rdata (m_axi_rdata[63:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../erx/hdl" "../../etx/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

155
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@ -1,155 +0,0 @@
/*
########################################################################
MASTER ENABLE, CLOCKS, CHIP-ID
########################################################################
*/
`include "elink_regmap.v"
module ecfg_elink (/*AUTOARG*/
// Outputs
txwr_gated_access, etx_soft_reset, erx_soft_reset, clk_config,
chipid,
// Inputs
clk, por_reset, txwr_access, txwr_packet
);
parameter RFAW = 6; // 32 registers for now
parameter PW = 104; // 32 registers for now
parameter ID = 12'h000;
parameter DEFAULT_CHIPID = 12'h808;
/******************************/
/*Clock/reset */
/******************************/
input clk;
input por_reset; // POR "hard reset"
/******************************/
/*REGISTER ACCESS */
/******************************/
input txwr_access;
input [PW-1:0] txwr_packet;
/******************************/
/*FILTERED WRITE FOR TX FIFO */
/******************************/
output txwr_gated_access;
/******************************/
/*Outputs */
/******************************/
output etx_soft_reset; // tx soft reset (level)
output erx_soft_reset; // rx soft reset (level)
output [15:0] clk_config; // clock settings (for pll)
output [11:0] chipid; // chip-id for Epiphany
/*------------------------CODE BODY---------------------------------------*/
//registers
reg [1:0] ecfg_reset_reg;
reg [15:0] ecfg_clk_reg;
reg [11:0] ecfg_chipid_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_clk_write;
wire ecfg_chipid_write;
wire ecfg_reset_write;
wire mi_en;
wire [31:0] mi_addr;
wire [31:0] mi_din;
packet2emesh pe2 (
// Outputs
.write_out (mi_we),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (mi_addr[31:0]),
.data_out (mi_din[31:0]),
.srcaddr_out (),
// Inputs
.packet_in (txwr_packet[PW-1:0])
);
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
assign mi_en = txwr_access &
(mi_addr[31:20]==ID) &
(mi_addr[10:8]==3'h2);
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
assign ecfg_chipid_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CHIPID);
/*****************************/
/*FILTER ACCESS */
/*****************************/
assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
ecfg_clk_write |
ecfg_chipid_write);
//###########################
//# RESET REG (ASYNC)
//###########################
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_reset_reg[1:0] <= 'b0;
else if (ecfg_reset_write)
ecfg_reset_reg[1:0] <= mi_din[1:0];
assign etx_soft_reset = ecfg_reset_reg[0];
assign erx_soft_reset = ecfg_reset_reg[1];
//###########################
//# CCLK/LCLK (PLL)
//###########################
//TODO: implement!
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
else if (ecfg_clk_write)
ecfg_clk_reg[15:0] <= mi_din[15:0];
assign clk_config[15:0] = ecfg_clk_reg[15:0];
//###########################
//# CHIPID
//###########################
always @ (posedge clk or posedge por_reset)
if(por_reset)
ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
else if (ecfg_chipid_write)
ecfg_chipid_reg[11:0] <= mi_din[11:0];
assign chipid[11:0]=ecfg_chipid_reg[5:2];
endmodule // ecfg_elink
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

182
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@ -1,182 +0,0 @@
/*
########################################################################
########################################################################
*/
module ecfg_if (/*AUTOARG*/
// Outputs
mi_mmu_en, mi_dma_en, mi_cfg_en, mi_we, mi_addr, mi_din,
access_out, packet_out,
// Inputs
clk, access_in, packet_in, mi_dout0, mi_dout1, mi_dout2, mi_dout3,
wait_in
);
parameter RX = 0; //0,1
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h810;
/********************************/
/*Clocks/reset */
/********************************/
input clk;
/********************************/
/*Incoming Packet */
/********************************/
input access_in;
input [PW-1:0] packet_in;
/********************************/
/* Register Interface */
/********************************/
output mi_mmu_en;
output mi_dma_en;
output mi_cfg_en;
output mi_we;
output [14:0] mi_addr;
output [63:0] mi_din;
input [63:0] mi_dout0;
input [63:0] mi_dout1;
input [63:0] mi_dout2;
input [63:0] mi_dout3;
/********************************/
/* Outgoing Packet */
/********************************/
output access_out;
output [PW-1:0] packet_out;
input wait_in; //incoming wait
//wires
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [63:0] mi_dout_mux;
wire mi_rd;
wire access_forward;
wire rxsel;
wire mi_en;
//regs;
reg access_out;
reg [31:0] dstaddr_reg;
reg [31:0] srcaddr_reg;
reg [1:0] datamode_reg;
reg [3:0] ctrlmode_reg;
reg write_reg;
reg readback_reg;
reg [31:0] data_reg;
wire [31:0] data_out;
//parameter didn't seem to work
assign rxsel = RX;
//splicing packet
packet2emesh p2e (
.write_out (write),
.datamode_out (datamode[1:0] ),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (packet_in[PW-1:0])
);
//ENABLE SIGNALS
assign mi_match = access_in & (dstaddr[31:20]==ID);
//config select (group 2 and 3)
assign mi_cfg_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]=={2'b01,rxsel});
//dma select (group 5)
assign mi_dma_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]==3'h5) &
(dstaddr[5]==rxsel);
//mmu select
assign mi_mmu_en = mi_match &
(dstaddr[19:16]==4'hE) &
(dstaddr[15]==rxsel);
//read/write indicator
assign mi_en = (mi_mmu_en | mi_cfg_en | mi_dma_en);
assign mi_rd = ~write & mi_en;
assign mi_we = write & mi_en;
//signal to carry transaction from ETX to ERX block through fifo_cdc
assign mi_rx_en = mi_match &
((dstaddr[19:16]==4'hE) | (dstaddr[19:16]==4'hF)) &
~mi_en;
//ADDR
assign mi_addr[14:0] = dstaddr[14:0];
//DIN
assign mi_din[63:0] = {srcaddr[31:0], data[31:0]};
//READBACK MUX (inputs should be zero if not used)
assign mi_dout_mux[63:0] = mi_dout0[63:0] |
mi_dout1[63:0] |
mi_dout2[63:0] |
mi_dout3[63:0];
//Access out packet
assign access_forward = (mi_rx_en | mi_rd);
always @ (posedge clk)
if(~wait_in)
access_out <= access_forward;
always @ (posedge clk)
if(~wait_in)
begin
readback_reg <= mi_rd;
write_reg <= (mi_rx_en & write) | mi_rd;
datamode_reg[1:0] <= datamode[1:0];
ctrlmode_reg[3:0] <= ctrlmode[3:0];
dstaddr_reg[31:0] <= mi_rx_en ? dstaddr[31:0] : srcaddr[31:0];
data_reg[31:0] <= data[31:0];
srcaddr_reg[31:0] <= mi_rx_en ? srcaddr[31:0] : mi_dout_mux[63:32];
end
assign data_out[31:0] = readback_reg ? mi_dout_mux[31:0] : data_reg[31:0];
//Create packet
emesh2packet e2p (.packet_out (packet_out[PW-1:0]),
.write_in (write_reg),
.datamode_in (datamode_reg[1:0]),
.ctrlmode_in (ctrlmode_reg[3:0]),
.dstaddr_in (dstaddr_reg[AW-1:0]),
.data_in (data_out[31:0]),
.srcaddr_in (srcaddr_reg[AW-1:0])
);
endmodule // ecfg_if
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

226
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@ -1,226 +0,0 @@
module edma (/*AUTOARG*/
// Outputs
mi_dout, edma_access, edma_packet,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, edma_wait
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6;
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; //async reset
input clk;
/*****************************/
/*REGISTER INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr;
input [63:0] mi_din;
output [31:0] mi_dout;
/*****************************/
/*DMA TRANSACTION */
/*****************************/
output edma_access;
output [PW-1:0] edma_packet;
input edma_wait;
assign edma_access=1'b0;
assign edma_packet='d0;
assign mi_dout='d0;
/*
//registers
reg [AW-1:0] edma_srcaddr_reg;
reg [AW-1:0] edma_dstaddr_reg;
reg [AW-1:0] edma_count_reg;
reg [AW-1:0] edma_stride_reg;
reg [8:0] edma_cfg_reg;
reg [1:0] edma_status_reg;
reg [31:0] mi_dout;
//wires
wire edma_write;
wire edma_read;
wire edma_cfg_write ;
wire edma_srcaddr_write;
wire edma_dstaddr_write;
wire edma_stride_write;
wire edma_count_write;
wire edma_message;
wire edma_expired;
wire edma_last_tran;
wire edma_error;
wire edma_enable;
//read/write decode
assign edma_write = mi_en & mi_we;
assign edma_read = mi_en & ~mi_we;
//DMA configuration
assign edma_cfg_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACFG);
assign edma_srcaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASRCADDR);
assign edma_dstaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMADSTADDR);
assign edma_count_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACOUNT);
assign edma_stride_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASTRIDE);
//###########################
//# DMACFG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_cfg_reg[8:0] <= 'd0;
else if (edma_cfg_write)
edma_cfg_reg[8:0] <= mi_din[8:0];
assign edma_enable = edma_cfg_reg[0]; //should be zero
assign edma_message = edma_cfg_reg[8];
assign edma_access = edma_enable & ~edma_expired;
assign edma_write = edma_cfg_reg[1]; //only 1 for test pattern
assign edma_datamode[1:0] = edma_cfg_reg[3:2];
assign edma_ctrlmode[3:0] = (edma_message & edma_last_tran) ? 4'b1100 : edma_cfg_reg[7:4];
//###########################
//# DMASTATUS
//###########################
//Misalignment
assign edma_error = ((edma_srcaddr_reg[0] | edma_dstaddr_reg[0]) & (edma_datamode[1:0]!=2'b00)) | //16/32/64
((edma_srcaddr_reg[1] | edma_dstaddr_reg[1]) & (edma_datamode[1])) | //32/64
((edma_srcaddr_reg[2] | edma_dstaddr_reg[2]) & (edma_datamode[1:0]==2'b11)); //64
always @ (posedge clk or posedge reset)
if(reset)
edma_status_reg[1:0] <= 'd0;
else if (edma_cfg_write)
edma_status_reg[1:0] <= mi_din[1:0];
else if (edma_enable)
begin
edma_status_reg[0] <= edma_enable & ~edma_expired;//dma busy
edma_status_reg[1] <= edma_status_reg[1] | (edma_enable & edma_error);
end
//###########################
//# EDMASRCADDR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_srcaddr_reg[AW-1:0] <= 'd0;
else if (edma_srcaddr_write)
edma_srcaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_srcaddr_reg[AW-1:0] <= edma_srcaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_srcaddr[31:0] = edma_srcaddr_reg[31:0];
//###########################
//# EDMADSTADR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_dstaddr_reg[AW-1:0] <= 'd0;
else if (edma_dstaddr_write)
edma_dstaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_dstaddr_reg[AW-1:0] <= edma_dstaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_dstaddr[31:0] = edma_dstaddr_reg[31:0];
//###########################
//# EDMACOUNT
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_count_reg[AW-1:0] <= 'd0;
else if (edma_count_write)
edma_count_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_count_reg[AW-1:0] <= edma_count_reg[AW-1:0] - 1'b1;
assign edma_last_tran = (edma_count_reg[AW-1:0]==32'b1);
assign edma_expired = (edma_count_reg[AW-1:0]==32'b0);
//###########################
//# EDMASTRIDE
//###########################
//NOTE: not supported yet, need to think about feature...
always @ (posedge clk or posedge reset)
if(reset)
edma_stride_reg[AW-1:0] <= 'd0;
else if (edma_stride_write)
edma_stride_reg[AW-1:0] <= mi_din[AW-1:0];
//###########################
//# DUMMY DATA
//###########################
assign edma_data[31:0] = TEST_PATTERN;
//###########################
//# PACKET CREATION
//###########################
emesh2packet e2p (
// Outputs
.packet_out (edma_packet[PW-1:0]),
// Inputs
.access_in (edma_access),
.write_in (edma_write),
.datamode_in (edma_datamode[1:0]),
.ctrlmode_in (edma_ctrlmode[3:0]),
.dstaddr_in (edma_dstaddr[AW-1:0]),
.data_in (edma_data[DW-1:0]),
.srcaddr_in (edma_srcaddr_in[AW-1:0]));
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(edma_read)
case(mi_addr[RFAW+1:2])
`EDMACFG: mi_dout[31:0] <= {23'b0, edma_cfg_reg[8:0]};
`EDMASTATUS: mi_dout[31:0] <= {30'b0, edma_status_reg[1:0]};
`EDMASRCADDR:mi_dout[31:0] <= {edma_srcaddr_reg[31:0]};
`EDMADSTADDR:mi_dout[31:0] <= {edma_dstaddr_reg[31:0]};
`EDMACOUNT: mi_dout[31:0] <= {edma_count_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
begin
default: mi_dout[31:0] <= 32'd0;
end
*/
endmodule // edma
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

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module elink (/*AUTOARG*/
// Outputs
elink_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, chipid, cclk_p, cclk_n, chip_resetb,
mailbox_not_empty, mailbox_full, timeout, rxwr_access, rxwr_packet,
rxrd_access, rxrd_packet, rxrr_access, rxrr_packet, txwr_wait,
txrd_wait, txrr_wait,
// Inputs
sys_reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait,
txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access,
txrr_packet
);
parameter AW = 32; //native address width
parameter DW = 32; //native data width
parameter PW = 104; //packet width
parameter ID = 12'h810; //epiphany ID for elink (ie addr[31:20])
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
/****************************/
/*CLOCK AND RESET */
/****************************/
input sys_reset; // reset for
input sys_clk; // single system clock for master/slave FIFOs
output elink_active; // rx and tx are both active
/********************************/
/*ELINK RECEIVER */
/********************************/
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
/********************************/
/*ELINK TRANSMITTER */
/********************************/
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback input
input txi_rd_wait_p,txi_rd_wait_n; // tx read pushback input
/*************************************/
/*EPIPHANY MISC INTERFACE (I/O PINS) */
/*************************************/
output [11:0] chipid; // chip id strap pins for epiphany
output cclk_p, cclk_n; //chip clock
output chip_resetb; // From etx of etx.v
/*****************************/
/*MAILBOX INTERRUPTS */
/*****************************/
output mailbox_not_empty;
output mailbox_full;
/*****************************/
/*TIMEOUT */
/*****************************/
output timeout;
/*****************************/
/*SYSTEM SIDE INTERFACE */
/*****************************/
//Master Write (from RX)
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//Master Read Request (from RX)
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//Slave Read Response (from RX)
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//Slave Write (to TX)
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Slave Read Request (to TX)
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Master Read Response (to TX)
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
/*#############################################*/
/* END OF BLOCK INTERFACE */
/*#############################################*/
/*AUTOINPUT*/
//wire
wire erx_cfg_access; // To erx of erx.v
wire [PW-1:0] erx_cfg_packet; // To erx of erx.v
wire etx_cfg_wait; // To etx of etx.v
wire [31:0] mi_rd_data;
wire [31:0] mi_dout_ecfg;
wire [31:0] mi_dout_embox;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire erx_cfg_wait; // From erx of erx.v
wire erx_reset; // From erx of erx.v
wire erx_soft_reset; // From ecfg_elink of ecfg_elink.v
wire etx_cfg_access; // From etx of etx.v
wire [PW-1:0] etx_cfg_packet; // From etx of etx.v
wire etx_reset; // From etx of etx.v
wire etx_soft_reset; // From ecfg_elink of ecfg_elink.v
wire rx_lclk_div4; // From erx of erx.v
wire tx_active; // From etx of etx.v
wire tx_lclk_div4; // From etx of etx.v
wire txwr_gated_access; // From ecfg_elink of ecfg_elink.v
// End of automatics
/***********************************************************/
/*CLOCK AND RESET CONFIG */
/***********************************************************/
defparam ecfg_elink.ID=ID;
ecfg_elink ecfg_elink (.clk (sys_clk),
.por_reset (sys_reset),
.clk_config (),
/*AUTOINST*/
// Outputs
.txwr_gated_access (txwr_gated_access),
.etx_soft_reset (etx_soft_reset),
.erx_soft_reset (erx_soft_reset),
.chipid (chipid[11:0]),
// Inputs
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]));
/***********************************************************/
/*RECEIVER */
/***********************************************************/
/*erx AUTO_TEMPLATE (
.mi_dout (mi_rx_dout[]),
.soft_reset (erx_soft_reset),
);
*/
defparam erx.ID = ID;
defparam erx.IOSTD_ELINK = IOSTD_ELINK;
defparam erx.ETYPE = ETYPE;
erx erx(.rx_active (elink_active),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.erx_cfg_wait (erx_cfg_wait),
.rx_lclk_div4 (rx_lclk_div4),
.erx_reset (erx_reset),
.timeout (timeout),
.mailbox_full (mailbox_full),
.mailbox_not_empty (mailbox_not_empty),
// Inputs
.soft_reset (erx_soft_reset), // Templated
.sys_reset (sys_reset),
.sys_clk (sys_clk),
.tx_active (tx_active),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
.erx_cfg_access (erx_cfg_access),
.erx_cfg_packet (erx_cfg_packet[PW-1:0]));
/***********************************************************/
/*TRANSMITTER */
/***********************************************************/
/*etx AUTO_TEMPLATE (.mi_dout (mi_tx_dout[]),
.emwr_\(.*\) (esaxi_emwr_\1[]),
.emrq_\(.*\) (esaxi_emrq_\1[]),
.emrr_\(.*\) (emaxi_emrr_\1[]),
.soft_reset (etx_soft_reset),
.txwr_access (txwr_gated_access),
);
*/
defparam etx.ID = ID;
defparam etx.IOSTD_ELINK = IOSTD_ELINK;
defparam etx.ETYPE = ETYPE;
etx etx(
/*AUTOINST*/
// Outputs
.tx_active (tx_active),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.chip_resetb (chip_resetb),
.txrd_wait (txrd_wait),
.txwr_wait (txwr_wait),
.txrr_wait (txrr_wait),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.etx_reset (etx_reset),
.tx_lclk_div4 (tx_lclk_div4),
// Inputs
.sys_clk (sys_clk),
.sys_reset (sys_reset),
.soft_reset (etx_soft_reset), // Templated
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txwr_access (txwr_gated_access), // Templated
.txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait));
/***********************************************************/
/*TX-->RX REGISTER INTERFACE CONNECTION */
/***********************************************************/
defparam ecfg_cdc.DW=104;
defparam ecfg_cdc.DEPTH=32;
fifo_cdc ecfg_cdc (.reset_in (etx_reset),
.reset_out (erx_reset),
// Outputs
.wait_out (etx_cfg_wait),
.access_out (erx_cfg_access),
.packet_out (erx_cfg_packet[PW-1:0]),
// Inputs
.clk_in (tx_lclk_div4),
.access_in (etx_cfg_access),
.packet_in (etx_cfg_packet[PW-1:0]),
.clk_out (rx_lclk_div4),
.wait_in (erx_cfg_wait)
);
endmodule
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

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parallella/fpga/parallella_base/parallella_base/src/elink_constants.v
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`ifndef ELINK_CONSTANTS_V_
`define ELINK_CONSTANTS_V_
//These constants are mutually exclusive
`define TARGET_XILINX //uncomment for non-xilinx platforms
`define CFG_AW 32
`define CFG_DW 32
`define CFG_LW 8
`define CFG_NW 13 /*Number of bytes in the transmission*/
`endif

49
parallella/fpga/parallella_base/parallella_base/src/elink_regmap.v
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`ifndef ELINK_REGMAP_V_
`define ELINK_REGMAP_V_
//MEMORY MAP
//[31:20] = LINKID
//[19:16] = GROUP SELECT
//[15] = MMU SELECT (for RX/TX)
//[14:11] = USED BY MMU ONLY
//[10:8] = register group
//[7:2] = REGISTER ADDRESS (0..63)
//[1:0] = IGNORED (no byte access)
//Link register groups addr[19:16]
`define EGROUP_MMR 4'hF // reserved for registers
`define EGROUP_MMU 4'hE // RX & TX MMU
`define EGROUP_RR 4'hD // read response block
//ETX-REGS
`define E_RESET 6'd0 //F0200-reset
`define E_CLK 6'd1 //F0204-clock configuration
`define E_CHIPID 6'd2 //F0208-Epiphany chip id for colid/rowid pins
`define E_VERSION 6'd3 //F020C-version #
`define ETX_CFG 6'd4 //F0210-config
`define ETX_STATUS 6'd5 //F0214-tx status
`define ETX_GPIO 6'd6 //F0218-direct data for tx pins
//ERX-REGS
`define ERX_CFG 6'd0 //F0300-config
`define ERX_STATUS 6'd1 //F0304-status register
`define ERX_GPIO 6'd2 //F0308-sampled data
`define ERX_OFFSET 6'd3 //F030C-memory base for remap
`define E_MAILBOXLO 6'd4 //F0310-reserved-->move?
`define E_MAILBOXHI 6'd5 //F0314-reserved
`define ERX_IDELAY0 6'd6 //F0318-tap delay for d[5:0]
`define ERX_IDELAY1 6'd7 //F031c-tap delays for {frame,d[7:6]}
`define ERX_TESTDATA 6'd8 //F0320-
//DMA (same numbering as in Epiphany, limit to 4 channels)
`define DMACFG 5'd0 //F0500/F0520
`define DMACOUNT 5'd1 //F0504/F0524
`define DMASTRIDE 5'd2 //F0508/F0528
`define DMASRCADDR 5'd3 //F050C/F052c
`define DMADSTADDR 5'd4 //F0510/F0530
`define DMAAUTO0 5'd5 //F0514/F0534
`define DMAAUTO1 5'd6 //F0518/F0538
`define DMASTATUS 5'd7 //F051C/F053c
`endif

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/*
###########################################################################
# Function: A mailbox FIFO with a FIFO empty/full flags that can be used as
# interrupts.
#
# E_MAILBOXLO = lower 32 bits of FIFO entry
# E_MAILBOXHI = upper 32 bits of FIFO entry
#
# Notes: 1.) System should take care of not overflowing the FIFO
# 2.) Reading the E_MAILBOXHI causes a fifo rd pointer update
# 3.) The "embox_not_empty" is a "level" interrupt signal.
#
# How to use: 1.) Connect "embox_not_empty" to interrupt input line
# 2.) Write an ISR to respond to interrupt line::
# -reads E_MAILBOXLO, then
# -reads E_MAILBOXHI, then
# -finishes ISR
#
###########################################################################
*/
`include "emailbox_regmap.v" // is there a better way?
module emailbox (/*AUTOARG*/
// Outputs
mi_dout, mailbox_full, mailbox_not_empty,
// Inputs
wr_reset, wr_clk, rd_clk, rd_reset, emesh_access, emesh_packet,
mi_en, mi_we, mi_addr, mi_din
);
parameter DW = 32; //data width of fifo
parameter AW = 32; //data width of fifo
parameter PW = 104; //packet size
parameter RFAW = 6; //address bus width
parameter ID = 12'h000; //link id
parameter WIDTH = 104;
parameter DEPTH = 16;
/*****************************/
/*RESET */
/*****************************/
input wr_reset; //asynchronous reset
input wr_clk; //write clock
input rd_clk; //read clock
input rd_reset; //asynchronous reset
/*****************************/
/*WRITE INTERFACE */
/*****************************/
input emesh_access;
input [PW-1:0] emesh_packet;
/*****************************/
/*READ INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr;
input [63:0] mi_din; //assumes write interface is 64 bits
output [63:0] mi_dout;
/*****************************/
/*MAILBOX OUTPUTS */
/*****************************/
output mailbox_full;
output mailbox_not_empty;
/*****************************/
/*REGISTERS */
/*****************************/
reg [63:0] mi_dout;
/*****************************/
/*WIRES */
/*****************************/
wire mailbox_read;
wire mi_rd;
wire [WIDTH-1:0] mailbox_fifo_data;
wire mailbox_empty;
wire mailbox_pop;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh__write;
/*****************************/
/*WRITE TO FIFO */
/*****************************/
assign emesh_addr[31:0] = emesh_packet[39:8];
assign emesh_din[63:0] = emesh_packet[103:40];
assign emesh_write = emesh_access &
emesh_packet[1] &
(emesh_addr[31:20]==ID) &
(emesh_addr[10:8]==3'h3) &
(emesh_addr[RFAW+1:2]==`E_MAILBOXLO);
/*****************************/
/*READ BACK DATA */
/*****************************/
assign mi_rd = mi_en & ~mi_we;
assign mailbox_pop = mi_rd & (mi_addr[RFAW+1:2]==`E_MAILBOXHI); //fifo read
always @ (posedge rd_clk)
if(mi_rd)
case(mi_addr[RFAW+1:2])
`E_MAILBOXLO: mi_dout[63:0] <= mailbox_fifo_data[63:0];
`E_MAILBOXHI: mi_dout[63:0] <= {mailbox_fifo_data[2*DW-1:DW],
mailbox_fifo_data[2*DW-1:DW]};
default: mi_dout[63:0] <= 64'd0;
endcase // case (mi_addr[RFAW-1:2])
else
mi_dout[63:0] <= 64'd0;
/*****************************/
/*FIFO (64bit wide) */
/*****************************/
assign mailbox_not_empty = ~mailbox_empty;
//BUG! This fifo is currently hard coded to 16 entries
//Should be parametrized to up to 4096 entries
defparam fifo.DW = WIDTH;
defparam fifo.DEPTH = DEPTH;
fifo_async fifo(// Outputs
.dout (mailbox_fifo_data[WIDTH-1:0]),
.empty (mailbox_empty),
.full (mailbox_full),
.prog_full (),
.valid(),
//Read Port
.rd_en (mailbox_pop),
.rd_clk (rd_clk),
//Write Port
.din ({40'b0,emesh_din[63:0]}),
.wr_en (emesh_write),
.wr_clk (wr_clk),
.wr_rst (wr_reset),
.rd_rst (rd_reset)
);
endmodule // emailbox
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

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parallella/fpga/parallella_base/parallella_base/src/emailbox_regmap.v
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`ifndef EMAILBOX_REGMAP_V_
`define EMAILBOX_REGMAP_V_
`ifndef E_MAILBOXLO
`define E_MAILBOXLO 6'd4
`endif
`ifndef E_MAILBOXHI
`define E_MAILBOXHI 6'd5
`endif
`endif

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parallella/fpga/parallella_base/parallella_base/src/emaxi.v
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/*
########################################################################
Epiphany eLink AXI Master Module
########################################################################
NOTES:
--write channels: write address, write data, write response
--read channels: read address, read data channel
--'valid' source signal used to show valid address,data,control is available
--'ready' destination ready signal indicates readyness to accept information
--'last' signal indicates the transfer of final data item
--read and write have separate address channels
--read data channel carries read data from slave to master
--write channel includes a byte lane strobe signal for every eight data bits
--there is no acknowledge on write, treated as buffered
--channels are unidirectional
--valid is asserted uncondotionally
--ready occurs cycle after valid
--there can be no combinatorial path between input and output of interface
--destination is permitted to wait for valud before asserting READY
--source is not allowed to wait for READY to assert VALID
--AWVALID must remain asserted until the rising clock edge after slave asserts AWREADY??
--The default state of AWREADY can be either HIGH or LOW. This specification recommends a default state of HIGH.
--During a write burst, the master can assert the WVALID signal only when it drives valid write data.
--The default state of WREADY can be HIGH, but only if the slave can always accept write data in a single cycle.
--The master must assert the WLAST signal while it is driving the final write transfer in the burst.
--_aw=write address channel
--_ar=read address channel
--_r=read data channel
--_w=write data channel
--_b=write response channel
*/
module emaxi(/*autoarg*/
// Outputs
rxwr_wait, rxrd_wait, txrr_access, txrr_packet, m_axi_awid,
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
// Inputs
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, txrr_wait,
m_axi_aclk, m_axi_aresetn, m_axi_awready, m_axi_wready, m_axi_bid,
m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid
);
parameter M_IDW = 12;
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
//########################
//ELINK INTERFACE
//########################
//Write request from erx
input rxwr_access;
input [PW-1:0] rxwr_packet;
output rxwr_wait;
//Read request from erx
input rxrd_access;
input [PW-1:0] rxrd_packet;
output rxrd_wait;
//Read respoonse for etx
output txrr_access;
output [PW-1:0] txrr_packet;
input txrr_wait;
//########################
//AXI MASTER INTERFACE
//########################
input m_axi_aclk; // global clock signal.
input m_axi_aresetn; // global reset singal.
//Write address channel
output [M_IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
output [1 : 0] m_axi_awburst; // burst type.
output [1 : 0] m_axi_awlock; // lock type
output [3 : 0] m_axi_awcache; // memory type.
output [2 : 0] m_axi_awprot; // protection type.
output [3 : 0] m_axi_awqos; // quality of service
output m_axi_awvalid; // write address valid
input m_axi_awready; // write address ready
//Write data channel
output [M_IDW-1:0] m_axi_wid;
output [63 : 0] m_axi_wdata; // master interface write data.
output [7 : 0] m_axi_wstrb; // byte write strobes
output m_axi_wlast; // indicates last transfer in a write burst.
output m_axi_wvalid; // indicates data is ready to go
input m_axi_wready; // indicates that the slave is ready for data
//Write response channel
input [M_IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // channel is signaling a valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [M_IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
output [1 : 0] m_axi_arburst; // burst type
output [1 : 0] m_axi_arlock; //lock type
output [3 : 0] m_axi_arcache; // memory type
output [2 : 0] m_axi_arprot; // protection type
output [3 : 0] m_axi_arqos; //
output m_axi_arvalid; // valid read address and control information
input m_axi_arready; // slave is ready to accept an address
//Read data channel
input [M_IDW-1:0] m_axi_rid;
input [63 : 0] m_axi_rdata; // master read data
input [1 : 0] m_axi_rresp; // status of the read transfer
input m_axi_rlast; // signals last transfer in a read burst
input m_axi_rvalid; // signaling the required read data
output m_axi_rready; // master can accept the readback data
//#########################################################################
//REGISTER/WIRE DECLARATIONS
//#########################################################################
reg [31 : 0] m_axi_awaddr;
reg [7:0] m_axi_awlen;
reg [2:0] m_axi_awsize;
reg m_axi_awvalid;
reg [63 : 0] m_axi_wdata;
reg [63 : 0] m_axi_rdata_reg;
reg [7 : 0] m_axi_wstrb;
reg m_axi_wlast;
reg m_axi_wvalid;
reg awvalid_b;
reg [31:0] awaddr_b;
reg [2:0] awsize_b;
reg [7:0] awlen_b;
reg wvalid_b;
reg [63:0] wdata_b;
reg [7:0] wstrb_b;
reg [63 : 0] wdata_aligned;
reg [7 : 0] wstrb_aligned;
reg txrr_access;
reg txrr_access_reg;
reg [31:0] txrr_data;
reg [31:0] txrr_srcaddr;
//wires
wire aw_go;
wire w_go;
wire readinfo_wren;
wire readinfo_full;
wire [47:0] readinfo_out;
wire [47:0] readinfo_in;
wire awvalid_in;
wire [1:0] rxwr_datamode;
wire [AW-1:0] rxwr_dstaddr;
wire [DW-1:0] rxwr_data;
wire [AW-1:0] rxwr_srcaddr;
wire [1:0] rxrd_datamode;
wire [3:0] rxrd_ctrlmode;
wire [AW-1:0] rxrd_dstaddr;
wire [AW-1:0] rxrd_srcaddr;
wire [1:0] txrr_datamode;
wire [3:0] txrr_ctrlmode;
wire [31:0] txrr_dstaddr;
//#########################################################################
//EMESH 2 PACKET CONVERSION
//#########################################################################
//RXWR
packet2emesh p2e_rxwr (
// Outputs
.write_out (),
.datamode_out (rxwr_datamode[1:0]),
.ctrlmode_out (),
.dstaddr_out (rxwr_dstaddr[AW-1:0]),
.data_out (rxwr_data[DW-1:0]),
.srcaddr_out (rxwr_srcaddr[AW-1:0]),
// Inputs
.packet_in (rxwr_packet[PW-1:0])
);
//RXRD
packet2emesh p2e_rxrd (
// Outputs
.write_out (),
.datamode_out (rxrd_datamode[1:0]),
.ctrlmode_out (rxrd_ctrlmode[3:0]),
.dstaddr_out (rxrd_dstaddr[AW-1:0]),
.data_out (),
.srcaddr_out (rxrd_srcaddr[AW-1:0]),
// Inputs
.packet_in (rxrd_packet[PW-1:0])
);
//TXRR
emesh2packet e2p (
// Outputs
.packet_out (txrr_packet[PW-1:0]),
// Inputs
.write_in (1'b1),
.datamode_in (txrr_datamode[1:0]),
.ctrlmode_in (txrr_ctrlmode[3:0]),
.dstaddr_in (txrr_dstaddr[AW-1:0]),
.data_in (txrr_data[DW-1:0]),
.srcaddr_in (txrr_srcaddr[AW-1:0])
);
//#########################################################################
//AXI unimplemented constants
//#########################################################################
assign m_axi_awburst[1:0] = 2'b01; //only increment burst supported
assign m_axi_awcache[3:0] = 4'b0000;//TODO: correct value??
assign m_axi_awprot[2:0] = 3'b000;
assign m_axi_awqos[3:0] = 4'b0000;
assign m_axi_awlock = 2'b00;
assign m_axi_arburst[1:0] = 2'b01; //only increment burst supported
assign m_axi_arcache[3:0] = 4'b0000;
assign m_axi_arprot[2:0] = 3'h0;
assign m_axi_arqos[3:0] = 4'h0;
assign m_axi_bready = 1'b1;//tie to wait signal????
//#########################################################################
//Write address channel
//#########################################################################
assign aw_go = m_axi_awvalid & m_axi_awready;
assign w_go = m_axi_wvalid & m_axi_wready;
assign rxwr_wait = awvalid_b | wvalid_b;
assign awvalid_in = rxwr_access & ~awvalid_b & ~wvalid_b;
// generate write-address signals
always @( posedge m_axi_aclk )
if(!m_axi_aresetn)
begin
m_axi_awvalid <= 1'b0;
m_axi_awaddr[31:0] <= 32'd0;
m_axi_awlen[7:0] <= 8'd0;
m_axi_awsize[2:0] <= 3'd0;
awvalid_b <= 1'b0;
awaddr_b <= 'd0;
awlen_b[7:0] <= 'd0;
awsize_b[2:0] <= 'd0;
end
else
begin
if( ~m_axi_awvalid | aw_go )
begin
if( awvalid_b )
begin
m_axi_awvalid <= 1'b1;
m_axi_awaddr[31:0] <= awaddr_b[31:0];
m_axi_awlen[7:0] <= awlen_b[7:0];
m_axi_awsize[2:0] <= awsize_b[2:0];
end
else
begin
m_axi_awvalid <= awvalid_in;
m_axi_awaddr[31:0] <= rxwr_dstaddr[31:0];
m_axi_awlen[7:0] <= 8'b0;
m_axi_awsize[2:0] <= { 1'b0, rxwr_datamode[1:0]};
end
end
if( awvalid_in & m_axi_awvalid & ~aw_go )
awvalid_b <= 1'b1;
else if( aw_go )
awvalid_b <= 1'b0;
//Pipeline stage
if( awvalid_in )
begin
awaddr_b[31:0] <= rxwr_dstaddr[31:0];
awlen_b[7:0] <= 8'b0;
awsize_b[2:0] <= { 1'b0, rxwr_datamode[1:0] };
end
end // else: !if(~m_axi_aresetn)
//#########################################################################
//Write data alignment circuit
//#########################################################################
always @*
case( rxwr_datamode[1:0] )
2'd0: wdata_aligned[63:0] = { 8{rxwr_data[7:0]}};
2'd1: wdata_aligned[63:0] = { 4{rxwr_data[15:0]}};
2'd2: wdata_aligned[63:0] = { 2{rxwr_data[31:0]}};
default: wdata_aligned[63:0] = { rxwr_srcaddr[31:0], rxwr_data[31:0]};
endcase
always @*
begin
case(rxwr_datamode[1:0])
2'd0: // byte
case(rxwr_dstaddr[2:0])
3'd0: wstrb_aligned[7:0] = 8'h01;
3'd1: wstrb_aligned[7:0] = 8'h02;
3'd2: wstrb_aligned[7:0] = 8'h04;
3'd3: wstrb_aligned[7:0] = 8'h08;
3'd4: wstrb_aligned[7:0] = 8'h10;
3'd5: wstrb_aligned[7:0] = 8'h20;
3'd6: wstrb_aligned[7:0] = 8'h40;
default: wstrb_aligned[7:0] = 8'h80;
endcase
2'd1: // 16b hword
case(rxwr_dstaddr[2:1])
2'd0: wstrb_aligned[7:0] = 8'h03;
2'd1: wstrb_aligned[7:0] = 8'h0c;
2'd2: wstrb_aligned[7:0] = 8'h30;
default: wstrb_aligned[7:0] = 8'hc0;
endcase
2'd2: // 32b word
if(rxwr_dstaddr[2])
wstrb_aligned[7:0] = 8'hf0;
else
wstrb_aligned[7:0] = 8'h0f;
2'd3:
wstrb_aligned[7:0] = 8'hff;
endcase // case (emwr_datamode[1:0])
end // always @ *
//#########################################################################
//Write data channel
//#########################################################################
always @ (posedge m_axi_aclk )
if(~m_axi_aresetn)
begin
m_axi_wvalid <= 1'b0;
m_axi_wdata[63:0] <= 64'b0;
m_axi_wstrb[7:0] <= 8'b0;
m_axi_wlast <= 1'b1; // TODO:bursts!!
wvalid_b <= 1'b0;
wdata_b[63:0] <= 64'b0;
wstrb_b[7:0] <= 8'b0;
end
else
begin
if( ~m_axi_wvalid | w_go )
begin
if( wvalid_b )
begin
m_axi_wvalid <= 1'b1;
m_axi_wdata[63:0] <= wdata_b[63:0];
m_axi_wstrb[7:0] <= wstrb_b[7:0];
end
else
begin
m_axi_wvalid <= awvalid_in;
m_axi_wdata[63:0] <= wdata_aligned[63:0];
m_axi_wstrb[7:0] <= wstrb_aligned[7:0];
end
end // if ( ~axi_wvalid | w_go )
if( rxwr_access & m_axi_wvalid & ~w_go )
wvalid_b <= 1'b1;
else if( w_go )
wvalid_b <= 1'b0;
if( awvalid_in )
begin
wdata_b[63:0] <= wdata_aligned[63:0];
wstrb_b[7:0] <= wstrb_aligned[7:0];
end
end // else: !if(~m_axi_aresetn)
//#########################################################################
//Read request channel
//#########################################################################
//1. read request comes in on ar channel
//2. use src address to match with writes coming back
//3. Assumes in order returns
assign readinfo_in[47:0] =
{
7'b0,
rxrd_srcaddr[31:0],//40:9
rxrd_dstaddr[2:0], //8:6
rxrd_ctrlmode[3:0],//5:2
rxrd_datamode[1:0]
};
fifo_sync
#(
// parameters
.AW (5),
.DW (48))
fifo_readinfo_i
(
// outputs
.rd_data (readinfo_out[47:0]),
.rd_empty (),
.wr_full (readinfo_full),
// inputs
.clk (m_axi_aclk),
.reset (~m_axi_aresetn),
.wr_data (readinfo_in[47:0]),
.wr_en (m_axi_arvalid & m_axi_arready),
.rd_en (m_axi_rready & m_axi_rvalid)
);
assign txrr_datamode[1:0] = readinfo_out[1:0];
assign txrr_ctrlmode[3:0] = readinfo_out[5:2];
assign txrr_dstaddr[31:0] = readinfo_out[40:9];
//#########################################################################
//Read address channel
//#########################################################################
assign m_axi_araddr[31:0] = rxrd_dstaddr[31:0];
assign m_axi_arsize[2:0] = {1'b0, rxrd_datamode[1:0]};
assign m_axi_arlen[7:0] = 8'd0;
assign m_axi_arvalid = rxrd_access & ~readinfo_full;
assign rxrd_wait = readinfo_full | ~m_axi_arready;
//#########################################################################
//Read response channel
//#########################################################################
assign m_axi_rready = ~txrr_wait; //pass through
always @( posedge m_axi_aclk )
if ( ~m_axi_aresetn )
m_axi_rdata_reg <= 'b0;
else
m_axi_rdata_reg <= m_axi_rdata;
always @( posedge m_axi_aclk )
if( ~m_axi_aresetn )
begin
txrr_data[31:0] <= 32'b0;
txrr_srcaddr[31:0] <= 32'b0;
txrr_access_reg <= 1'b0;
txrr_access <= 1'b0;
end
else
begin
txrr_access_reg <= m_axi_rready & m_axi_rvalid;
txrr_access <= txrr_access_reg;//added pipeline stage for data
// steer read data according to size & host address lsbs
//all data needs to be right aligned
//(this is due to the Epiphany right aligning all words)
case(readinfo_out[1:0])//datamode
2'd0: // byte read
case(readinfo_out[8:6])
3'd0: txrr_data[7:0] <= m_axi_rdata_reg[7:0];
3'd1: txrr_data[7:0] <= m_axi_rdata_reg[15:8];
3'd2: txrr_data[7:0] <= m_axi_rdata_reg[23:16];
3'd3: txrr_data[7:0] <= m_axi_rdata_reg[31:24];
3'd4: txrr_data[7:0] <= m_axi_rdata_reg[39:32];
3'd5: txrr_data[7:0] <= m_axi_rdata_reg[47:40];
3'd6: txrr_data[7:0] <= m_axi_rdata_reg[55:48];
default: txrr_data[7:0] <= m_axi_rdata_reg[63:56];
endcase
2'd1: // 16b hword
case( readinfo_out[8:7] )
2'd0: txrr_data[15:0] <= m_axi_rdata_reg[15:0];
2'd1: txrr_data[15:0] <= m_axi_rdata_reg[31:16];
2'd2: txrr_data[15:0] <= m_axi_rdata_reg[47:32];
default: txrr_data[15:0] <= m_axi_rdata_reg[63:48];
endcase
2'd2: // 32b word
if( readinfo_out[8] )
txrr_data[31:0] <= m_axi_rdata_reg[63:32];
else
txrr_data[31:0] <= m_axi_rdata_reg[31:0];
// 64b word already defined by defaults above
2'd3:
begin // 64b dword
txrr_data[31:0] <= m_axi_rdata_reg[31:0];
txrr_srcaddr[31:0] <= m_axi_rdata_reg[63:32];
end
endcase
end // else: !if( ~m_axi_aresetn )
endmodule // emaxi
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../memory/hdl")
// End:
/*
copyright (c) 2014 adapteva, inc.
contributed by fred huettig <fred@adapteva.com>
contributed by andreas olofsson <andreas@adapteva.com>
this program is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
this program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with this program (see the file copying). if not, see
<http://www.gnu.org/licenses/>.
*/

50
parallella/fpga/parallella_base/parallella_base/src/emesh2packet.v
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@ -1,50 +0,0 @@
/*Converts an emesh bundle into a 104 bit packet*/
module emesh2packet(/*AUTOARG*/
// Outputs
packet_out,
// Inputs
write_in, datamode_in, ctrlmode_in, dstaddr_in, data_in,
srcaddr_in
);
parameter AW=32;
parameter DW=32;
parameter PW=104;
//Emesh signal bundle
input write_in;
input [1:0] datamode_in;
input [3:0] ctrlmode_in;
input [AW-1:0] dstaddr_in;
input [DW-1:0] data_in;
input [AW-1:0] srcaddr_in;
//Output packet
output [PW-1:0] packet_out;
assign packet_out[0] = write_in;
assign packet_out[2:1] = datamode_in[1:0];
assign packet_out[7:3] = {1'b0,ctrlmode_in[3:0]};
assign packet_out[39:8] = dstaddr_in[AW-1:0];
assign packet_out[71:40] = data_in[AW-1:0];
assign packet_out[103:72] = srcaddr_in[AW-1:0];
endmodule // emesh2packet
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

163
parallella/fpga/parallella_base/parallella_base/src/emmu.v
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@ -1,163 +0,0 @@
/*
###########################################################################
# **EMMU**
#
# This block uses the upper 12 bits [31:20] of a memory address as an index
# to read an entry from a table.
#
# The table is written from the mi_* configuration interface.
#
# The table can be configured as 12 bits wide or 44 bits wide.
#
# 32bit address output = {table_data[11:0],dstaddr[19:0]}
# 64bit address output = {table_data[43:0],dstaddr[19:0]}
#
############################################################################
*/
module emmu (/*AUTOARG*/
// Outputs
mi_dout, emesh_access_out, emesh_packet_out, emesh_packet_hi_out,
// Inputs
rd_clk, wr_clk, mmu_en, mmu_bp, mi_en, mi_we, mi_addr, mi_din,
emesh_access_in, emesh_packet_in, emesh_wait
);
parameter DW = 32; //data width
parameter AW = 32; //address width
parameter PW = 104;
parameter EPW = 136; //extended by 32 bits
parameter MW = 48; //width of table
parameter MAW = 12; //memory addres width (entries = 1<<MAW)
parameter GROUP = 0;
/*****************************/
/*DATAPATH CLOCk */
/*****************************/
input rd_clk;
input wr_clk;
/*****************************/
/*MMU LOOKUP DATA */
/*****************************/
input mmu_en; //enables mmu (static)
input mmu_bp; //bypass mmu on read response (RX)
/*****************************/
/*Register Access Interface */
/*****************************/
input mi_en; //memory access
input mi_we; //byte wise write enable
input [14:0] mi_addr; //address
input [DW-1:0] mi_din; //input data
output [DW-1:0] mi_dout; //read back (TODO?? not implemented)
/*****************************/
/*EMESH INPUTS */
/*****************************/
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
input emesh_wait; //BUG?: separate wait fifos?
/*****************************/
/*EMESH OUTPUTS */
/*****************************/
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
output [31:0] emesh_packet_hi_out;
/*****************************/
/*REGISTERS */
/*****************************/
reg emesh_access_out;
reg [PW-1:0] emesh_packet_reg;
wire [63:0] emesh_dstaddr_out;
wire [MW-1:0] emmu_lookup_data;
wire [63:0] mi_wr_data;
wire [5:0] mi_wr_vec;
wire mi_match;
wire [MW-1:0] emmu_rd_addr;
wire write_in;
/*****************************/
/*MMU WRITE LOGIC */
/*****************************/
//write controls
assign mi_wr_vec[5:0] = (mi_en & mi_we & ~mi_addr[2]) ? 6'b001111 :
(mi_en & mi_we & mi_addr[2]) ? 6'b110000 :
6'b000000 ;
//write data
assign mi_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
//todo: implement readback? worth it?
assign mi_dout[DW-1:0] = 'b0;
/*****************************/
/*MMU READ LOGIC */
/*****************************/
assign write_in = emesh_packet_in[1]; //TODO:
assign emmu_rd_addr[MAW-1:0] = emesh_packet_in[39:28];
memory_dp #(.DW(MW),.AW(MAW)) memory_dp (
// Outputs
.rd_data (emmu_lookup_data[MW-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_en (mi_wr_vec[5:0]),
.wr_addr (mi_addr[14:3]),
.wr_data (mi_wr_data[MW-1:0]),
.rd_clk (rd_clk),
.rd_en (emesh_access_in),
.rd_addr (emmu_rd_addr[MAW-1:0])
);
/*****************************/
/*EMESH OUTPUT TRANSACTION */
/*****************************/
//pipeline to compensate for table lookup pipeline
//assumes one cycle memory access!
//the pushback is needed stall async transmit path
always @ (posedge rd_clk)
if(~emesh_wait)
begin
emesh_access_out <= emesh_access_in;
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];
end
assign emesh_dstaddr_out[63:0] = (mmu_en & ~mmu_bp) ? {emmu_lookup_data[43:0], emesh_packet_reg[27:8]} :
{32'b0,emesh_packet_reg[39:8]};
//Concatenating output packet
assign emesh_packet_out[PW-1:0] = {emesh_packet_reg[PW-1:40],
emesh_dstaddr_out[31:0],
emesh_packet_reg[7:0]
};
assign emesh_packet_hi_out[31:0] = emesh_dstaddr_out[63:32];
endmodule // emmu
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

231
parallella/fpga/parallella_base/parallella_base/src/erx.v
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@ -1,231 +0,0 @@
module erx (/*AUTOARG*/
// Outputs
rx_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
rxrr_access, rxrr_packet, erx_cfg_wait, rx_lclk_div4, erx_reset,
timeout, mailbox_full, mailbox_not_empty,
// Inputs
soft_reset, sys_reset, sys_clk, tx_active, rxi_lclk_p, rxi_lclk_n,
rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rxwr_wait,
rxrd_wait, rxrr_wait, erx_cfg_access, erx_cfg_packet
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h800;
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
//Synched resets, clock
input soft_reset; // sw driven reset
input sys_reset; // async reset
input sys_clk; // system clock for fifo/clocks
input tx_active; // holds rx in check until tx has booted
output rx_active; // indicates RX and TX are active
//FROM IO Pins
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
//Master write
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//Master read request
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//Slave read response
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//Configuration Interface (from ETX)
input erx_cfg_access;
input [PW-1:0] erx_cfg_packet;
output erx_cfg_wait;
output rx_lclk_div4;
output erx_reset;
//Readback timeout (synchronized to sys_c
output timeout;
output mailbox_full;
output mailbox_not_empty;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire erx_io_reset; // From erx_clocks of erx_clocks.v
wire [44:0] idelay_value; // From erx_core of erx_core.v
wire load_taps; // From erx_core of erx_core.v
wire rx_access; // From erx_io of erx_io.v
wire rx_burst; // From erx_io of erx_io.v
wire rx_clkin; // From erx_io of erx_io.v
wire rx_lclk; // From erx_clocks of erx_clocks.v
wire [PW-1:0] rx_packet; // From erx_io of erx_io.v
wire rx_rd_wait; // From erx_core of erx_core.v
wire rx_wr_wait; // From erx_core of erx_core.v
wire rxrd_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxrd_fifo_packet; // From erx_core of erx_core.v
wire rxrd_fifo_wait; // From erx_fifo of erx_fifo.v
wire rxrr_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxrr_fifo_packet; // From erx_core of erx_core.v
wire rxrr_fifo_wait; // From erx_fifo of erx_fifo.v
wire rxwr_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxwr_fifo_packet; // From erx_core of erx_core.v
wire rxwr_fifo_wait; // From erx_fifo of erx_fifo.v
// End of automatics
/***********************************************************/
/*CLOCK/RESET */
/***********************************************************/
erx_clocks erx_clocks(/*AUTOINST*/
// Outputs
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.rx_active (rx_active),
.erx_reset (erx_reset),
.erx_io_reset (erx_io_reset),
// Inputs
.sys_reset (sys_reset),
.soft_reset (soft_reset),
.tx_active (tx_active),
.sys_clk (sys_clk),
.rx_clkin (rx_clkin));
/***********************************************************/
/*RECEIVER I/O LOGIC */
/***********************************************************/
defparam erx_io.IOSTD_ELINK=IOSTD_ELINK;
defparam erx_io.ETYPE=ETYPE;
erx_io erx_io (
/*AUTOINST*/
// Outputs
.rx_clkin (rx_clkin),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.rx_access (rx_access),
.rx_burst (rx_burst),
.rx_packet (rx_packet[PW-1:0]),
// Inputs
.erx_io_reset (erx_io_reset),
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.idelay_value (idelay_value[44:0]),
.load_taps (load_taps),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.rx_wr_wait (rx_wr_wait),
.rx_rd_wait (rx_rd_wait));
/**************************************************************/
/*ELINK CORE LOGIC */
/**************************************************************/
/*erx_core AUTO_TEMPLATE ( .rx_packet (rx_packet[PW-1:0]),
.rx_access (rx_access),
.erx_cfg_access (erx_cfg_access),
.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
.erx_cfg_wait (erx_cfg_wait),
.rx_rd_wait (rx_rd_wait),
.rx_wr_wait (rx_wr_wait),
.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
.\(.*\)_access (\1_fifo_access),
.\(.*\)_wait (\1_fifo_wait),
);
*/
defparam erx_core.ID=ID;
erx_core erx_core ( .clk (rx_lclk_div4),
.reset (erx_reset),
/*AUTOINST*/
// Outputs
.rx_rd_wait (rx_rd_wait), // Templated
.rx_wr_wait (rx_wr_wait), // Templated
.idelay_value (idelay_value[44:0]),
.load_taps (load_taps),
.rxrd_access (rxrd_fifo_access), // Templated
.rxrd_packet (rxrd_fifo_packet[PW-1:0]), // Templated
.rxrr_access (rxrr_fifo_access), // Templated
.rxrr_packet (rxrr_fifo_packet[PW-1:0]), // Templated
.rxwr_access (rxwr_fifo_access), // Templated
.rxwr_packet (rxwr_fifo_packet[PW-1:0]), // Templated
.erx_cfg_wait (erx_cfg_wait), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
// Inputs
.rx_packet (rx_packet[PW-1:0]), // Templated
.rx_access (rx_access), // Templated
.rx_burst (rx_burst),
.rxrd_wait (rxrd_fifo_wait), // Templated
.rxrr_wait (rxrr_fifo_wait), // Templated
.rxwr_wait (rxwr_fifo_wait), // Templated
.erx_cfg_access (erx_cfg_access), // Templated
.erx_cfg_packet (erx_cfg_packet[PW-1:0])); // Templated
/************************************************************/
/*FIFOs */
/************************************************************/
erx_fifo erx_fifo (
/*AUTOINST*/
// Outputs
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.rxrd_fifo_wait (rxrd_fifo_wait),
.rxrr_fifo_wait (rxrr_fifo_wait),
.rxwr_fifo_wait (rxwr_fifo_wait),
// Inputs
.erx_reset (erx_reset),
.sys_reset (sys_reset),
.rx_lclk_div4 (rx_lclk_div4),
.sys_clk (sys_clk),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
.rxrd_fifo_access(rxrd_fifo_access),
.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
.rxrr_fifo_access(rxrr_fifo_access),
.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
.rxwr_fifo_access(rxwr_fifo_access),
.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]));
endmodule // erx
// Local Variables:
// verilog-library-directories:(".")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

136
parallella/fpga/parallella_base/parallella_base/src/erx_arbiter.v
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@ -1,136 +0,0 @@
`include "elink_regmap.v"
module erx_arbiter (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,
rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
// Inputs
erx_rr_access, erx_packet, emmu_access, emmu_packet, edma_access,
edma_packet, ecfg_access, ecfg_packet, timeout, rxwr_wait,
rxrd_wait, rxrr_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h800; //link id
parameter RFAW = 6;
//From IO (for rr)
input erx_rr_access;
input [PW-1:0] erx_packet;
output rx_rd_wait; //for IO
output rx_wr_wait; //for IO
//From EMMU (writes)
input emmu_access;
input [PW-1:0] emmu_packet;
//From DMA
input edma_access;
input [PW-1:0] edma_packet;
output edma_wait;
//From ETX
input ecfg_access;
input [PW-1:0] ecfg_packet;
output ecfg_wait;
//From timeout circuit
input timeout;
//To Master Write FIFO
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//To Master Read FIFO
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//To Slave Read Response FIFO
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//wires
wire emmu_write;
wire emmu_read;
wire [11:0] myid;
//####################################
//Splicing pakets
//####################################
assign myid[11:0] = ID;
//####################################
//Read response path (from IO or cfg)
//####################################
assign rxrr_access = erx_rr_access |
ecfg_access;
assign rxrr_packet[PW-1:0] = erx_rr_access ? erx_packet[PW-1:0] :
ecfg_packet[PW-1:0];
assign ecfg_wait = erx_rr_access;
//####################################
//Write Path (through MMU)
//####################################
assign emmu_write = emmu_packet[0];
assign rxwr_access = emmu_access & emmu_write;
assign rxwr_packet[PW-1:0] = emmu_packet[PW-1:0];
//####################################
//Read Request Path
//####################################
assign emmu_read = emmu_access & ~emmu_write;
assign rxrd_access = emmu_read | edma_access;
assign rxrd_packet[PW-1:0] = emmu_read ? emmu_packet[PW-1:0] :
edma_packet[PW-1:0];
//####################################
//Wait Signals
//####################################
assign rx_rd_wait = rxrd_wait;
assign rx_wr_wait = rxwr_wait | rxrr_wait;
assign edma_wait = rxrd_wait | emmu_read;
assign erx_cfg_wait = rxwr_wait | rxrr_wait;
endmodule // erx_arbiter
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../emmu/hdl")
// End:
//#############################################################################
/*
This file is part of the Parallella Project.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

206
parallella/fpga/parallella_base/parallella_base/src/erx_cfg.v
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@ -1,206 +0,0 @@
// ########################################################################
// ELINK CONFIGURATION REGISTER FILE
// ########################################################################
`include "elink_regmap.v"
module erx_cfg (/*AUTOARG*/
// Outputs
mi_dout, rx_enable, mmu_enable, remap_mode, remap_base,
remap_pattern, remap_sel, timer_cfg, idelay_value, load_taps,
test_mode,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, erx_test_access,
erx_test_data, gpio_datain, rx_status
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6; // 32 registers for now
parameter GROUP = 4'h0;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; // ecfg registers reset only by "hard reset"
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_en;
input mi_we; // single we, must write 32 bit words
input [14:0] mi_addr; // complete physical address (no shifting!)
input [31:0] mi_din;
output [31:0] mi_dout;
//test interface
input erx_test_access;
input [31:0] erx_test_data;
/*****************************/
/*CONFIG SIGNALS */
/*****************************/
//rx
output rx_enable; // enable signal for rx
output mmu_enable; // enables MMU on rx path (static)
input [8:0] gpio_datain; // frame and data inputs (static)
input [15:0] rx_status; // etx status signals
output [1:0] remap_mode; // remap mode (static)
output [31:0] remap_base; // base for dynamic remap (static)
output [11:0] remap_pattern; // patter for static remap (static)
output [11:0] remap_sel; // selects for static remap (static)
output [1:0] timer_cfg; // timeout config (00=off) (static)
output [44:0] idelay_value; // tap values for erx idelay
output load_taps; // loads the idelay_value into IDELAY prim
output test_mode; // testmode blocks all rx ports to fifo
/*------------------------CODE BODY---------------------------------------*/
//registers
reg [31:0] ecfg_rx_reg;
reg [31:0] ecfg_offset_reg;
reg [8:0] ecfg_gpio_reg;
reg [2:0] ecfg_rx_status_reg;
reg [63:0] idelay_reg;
reg load_taps;
reg [31:0] mi_dout;
reg [31:0] ecfg_testdata_reg;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_rx_write;
wire ecfg_offset_write;
wire ecfg_remap_write;
wire ecfg_idelay0_write;
wire ecfg_idelay1_write;
wire ecfg_testdata_write;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_CFG);
assign ecfg_offset_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_OFFSET);
assign ecfg_idelay0_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_IDELAY0);
assign ecfg_idelay1_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_IDELAY1);
assign ecfg_testdata_write = ecfg_write & (mi_addr[RFAW+1:2]==`ERX_TESTDATA);
//###########################
//# RXCFG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
ecfg_rx_reg[31:0] <= 'b0;
else if (ecfg_rx_write)
ecfg_rx_reg[31:0] <= mi_din[31:0];
assign test_mode = ecfg_rx_reg[0];
assign mmu_enable = ecfg_rx_reg[1];
assign remap_mode[1:0] = ecfg_rx_reg[3:2];
assign remap_sel[11:0] = ecfg_rx_reg[15:4];
assign remap_pattern[11:0] = ecfg_rx_reg[27:16];
assign timer_cfg[1:0] = ecfg_rx_reg[29:28];
//###########################
//# DATAIN
//###########################
always @ (posedge clk)
ecfg_gpio_reg[8:0] <= gpio_datain[8:0];
//###########################1
//# DEBUG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
ecfg_rx_status_reg[2:0] <= 'b0;
else
ecfg_rx_status_reg[2:0] <= ecfg_rx_status_reg[2:0] | rx_status[2:0];
//###########################1
//# DYNAMIC REMAP BASE
//###########################
always @ (posedge clk)
if (ecfg_offset_write)
ecfg_offset_reg[31:0] <= mi_din[31:0];
assign remap_base[31:0] = ecfg_offset_reg[31:0];
//###########################1
//# IDELAY TAP VALUES
//###########################
always @ (posedge clk or posedge reset)
if(reset)
idelay_reg[63:0] <= 'b0;
else if (ecfg_idelay0_write)
idelay_reg[31:0] <= mi_din[31:0];
else if(ecfg_idelay1_write)
idelay_reg[63:32] <= mi_din[31:0];
//Construct delay for io (5*9 bits)
assign idelay_value[44:0] = {idelay_reg[44],idelay_reg[35:32],//frame
idelay_reg[43],idelay_reg[31:28],//d7
idelay_reg[42],idelay_reg[27:24],//d6
idelay_reg[41],idelay_reg[23:20],//d5
idelay_reg[40],idelay_reg[19:16],//d4
idelay_reg[39],idelay_reg[15:12],//d3
idelay_reg[38],idelay_reg[11:8], //d2
idelay_reg[37],idelay_reg[7:4], //d1
idelay_reg[36],idelay_reg[3:0] //d0
};
always @ (posedge clk)
load_taps <= ecfg_idelay1_write;
//###############################
//# TESTMODE (ADD OR LFSR
//###############################
wire testmode_add;
wire testmode_lfsr;
always @ (posedge clk)
if(ecfg_testdata_write)
ecfg_testdata_reg[31:0] <= mi_din[31:0];
else if(erx_test_access)
ecfg_testdata_reg[31:0] <= ecfg_testdata_reg[31:0] + erx_test_data[31:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ERX_CFG: mi_dout[31:0] <= {ecfg_rx_reg[31:0]};
`ERX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_gpio_reg[8:0]};
`ERX_STATUS: mi_dout[31:0] <= {16'b0, rx_status[15:3],ecfg_rx_status_reg[2:0]};
`ERX_OFFSET: mi_dout[31:0] <= {ecfg_offset_reg[31:0]};
`ERX_TESTDATA: mi_dout[31:0] <= {ecfg_testdata_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_rx
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

249
parallella/fpga/parallella_base/parallella_base/src/erx_clocks.v
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@ -1,249 +0,0 @@
`include "elink_constants.v"
module erx_clocks (/*AUTOARG*/
// Outputs
rx_lclk, rx_lclk_div4, rx_active, erx_reset, erx_io_reset,
// Inputs
sys_reset, soft_reset, tx_active, sys_clk, rx_clkin
);
`ifdef TARGET_SIMPLE
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_RXCLK = 300;
parameter FREQ_IDELAY = 200;
parameter RXCLK_PHASE = 0; //270; //-90 deg rxclk phase shift
parameter PLL_VCO_MULT = 4; //RX
//Don't touch these! (derived parameters)
localparam real RXCLK_PERIOD = 1000.000000/FREQ_RXCLK;
localparam integer IREF_DIVIDE = PLL_VCO_MULT * FREQ_RXCLK/FREQ_IDELAY;
localparam integer RXCLK_DIVIDE = PLL_VCO_MULT; //1:1
//Input clock, reset, config interface
input sys_reset; // por reset (hw)
input soft_reset; // rx enable signal (sw)
input tx_active; // tx active input
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
input rx_clkin; // input clk for RX only PLL
//RX Clocks
output rx_lclk; // rx high speed clock for DDR IO
output rx_lclk_div4; // rx slow clock for logic
//Reset
output rx_active; // rx active
output erx_reset; // reset for rx core logic
output erx_io_reset; // io reset (synced to high speed clock)
//############
//# WIRES
//############
//Idelay controller
wire idelay_reset;
wire idelay_ready; //ignore this?
wire idelay_ref_clk;
//pll outputs
wire rx_lclk_pll;
wire rx_lclk_div4_pll;
wire idelay_ref_clk_pll;
//PLL
wire rx_lclk_fb;
// wire rx_lclk_fb_out;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
reg pll_locked_reg;
reg pll_locked_sync;
reg [2:0] reset_state;
wire pll_reset;
reg [1:0] reset_pipe_lclkb;
reg [1:0] reset_pipe_lclk_div4b;
//wrap around counter that generates a 1 cycle heartbeat
//free running counter...
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
//two clock synchronizer
always @ (posedge sys_clk)
begin
pll_locked_reg <= pll_locked;
pll_locked_sync <= pll_locked_reg;
end
`define RESET_ALL 3'b000
`define START_PLL 3'b001
`define ACTIVE 3'b010
//Reset sequence state machine
always @ (posedge sys_clk or posedge reset_in)
if(reset_in)
reset_state[2:0] <= `RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`RESET_ALL :
if(~soft_reset)
reset_state[2:0] <= `START_PLL;
`START_PLL :
if(pll_locked_sync & idelay_ready)
reset_state[2:0] <= `ACTIVE;
`ACTIVE:
if(soft_reset)
reset_state[2:0] <= `RESET_ALL; //stay there until next reset
endcase // case (reset_state[2:0])
//reset PLL during 'reset' and during quiet time around reset edge
assign reset_in = sys_reset | ~tx_active;
assign pll_reset = (reset_state[2:0]==`RESET_ALL);
assign idelay_reset = (reset_state[2:0]==`RESET_ALL);
//asynch rx reset
assign rx_reset = (reset_state[2:0] != `ACTIVE);
//active indicator
assign rx_active = (reset_state[2:0] == `ACTIVE);
//#############################
//#RESET SYNC
//#############################
//async assert
//sync deassert
//lclk sync
always @ (posedge rx_lclk or posedge rx_reset)
if(rx_reset)
reset_pipe_lclkb[1:0] <= 2'b00;
else
reset_pipe_lclkb[1:0] <= {reset_pipe_lclkb[0], 1'b1};
assign erx_io_reset = ~reset_pipe_lclkb[1];
//lclkdiv4 sync
always @ (posedge rx_lclk_div4 or posedge rx_reset)
if(rx_reset)
reset_pipe_lclk_div4b[1:0] <= 2'b00;
else
reset_pipe_lclk_div4b[1:0] <= {reset_pipe_lclk_div4b[0],1'b1};
assign erx_reset = ~reset_pipe_lclk_div4b[1];
`ifdef TARGET_XILINX
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(IREF_DIVIDE), // idelay ref clk
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),//RXCLK_PHASE
.CLKOUT5_PHASE(0.0),//RXCLK_PHASE/4
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(idelay_ref_clk_pll),
.CLKOUT4(rx_lclk_pll),
.CLKOUT5(rx_lclk_div4_pll),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(rx_lclk_fb),
.CLKFBOUT(rx_lclk_fb),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(pll_locked)
);
//Clock network
BUFG i_lclk_bufg (.I(rx_lclk_pll), .O(rx_lclk)); //300Mhz
BUFG i_lclk_div4_bufg (.I(rx_lclk_div4_pll), .O(rx_lclk_div4)); //75 MHz (300/4)
BUFG i_idelay__bufg (.I(idelay_ref_clk_pll),.O(idelay_ref_clk));//idelay ctrl clock
// BUFG i_lclk_fb_bufg (.I(rx_lclk_fb_out), .O(rx_lclk_fb_in)); //feedback buffer
//###########################
// Idelay controller
//###########################
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset));
`endif // `ifdef TARGET_XILINX
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

393
parallella/fpga/parallella_base/parallella_base/src/erx_core.v
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@ -1,393 +0,0 @@
module erx_core (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, idelay_value, load_taps, rxrd_access,
rxrd_packet, rxrr_access, rxrr_packet, rxwr_access, rxwr_packet,
erx_cfg_wait, mailbox_full, mailbox_not_empty,
// Inputs
reset, clk, rx_packet, rx_access, rx_burst, rxrd_wait, rxrr_wait,
rxwr_wait, erx_cfg_access, erx_cfg_packet
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h800;
//clock and reset
input reset; //synced to clk
input clk;
//IO Interface
input [PW-1:0] rx_packet;
input rx_access;
input rx_burst;
output rx_rd_wait;
output rx_wr_wait;
output [44:0] idelay_value;
output load_taps;
//FIFO Access
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//register interface
input erx_cfg_access;
input [PW-1:0] erx_cfg_packet;
output erx_cfg_wait;
//mailbox outputs
output mailbox_full; //need to sync to sys_clk
output mailbox_not_empty; //need to sync to sys_clk
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ecfg_access; // From erx_cfgif of ecfg_if.v
wire [PW-1:0] ecfg_packet; // From erx_cfgif of ecfg_if.v
wire edma_access; // From erx_dma of edma.v
wire edma_wait; // From erx_arbiter of erx_arbiter.v
wire emesh_remap_access; // From erx_remap of erx_remap.v
wire [PW-1:0] emesh_remap_packet; // From erx_remap of erx_remap.v
wire emmu_access; // From erx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From erx_mmu of emmu.v
wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v
wire erx_rdwr_access; // From erx_protocol of erx_protocol.v
wire erx_rr_access; // From erx_protocol of erx_protocol.v
wire erx_test_access; // From erx_protocol of erx_protocol.v
wire [31:0] erx_test_data; // From erx_protocol of erx_protocol.v
wire [14:0] mi_addr; // From erx_cfgif of ecfg_if.v
wire [DW-1:0] mi_cfg_dout; // From erx_cfg of erx_cfg.v
wire mi_cfg_en; // From erx_cfgif of ecfg_if.v
wire [63:0] mi_din; // From erx_cfgif of ecfg_if.v
wire [DW-1:0] mi_dma_dout; // From erx_dma of edma.v
wire mi_dma_en; // From erx_cfgif of ecfg_if.v
wire [63:0] mi_mailbox_dout; // From erx_mailbox of emailbox.v
wire [DW-1:0] mi_mmu_dout; // From erx_mmu of emmu.v
wire mi_mmu_en; // From erx_cfgif of ecfg_if.v
wire mi_we; // From erx_cfgif of ecfg_if.v
wire mmu_enable; // From erx_cfg of erx_cfg.v
wire [31:0] remap_base; // From erx_cfg of erx_cfg.v
wire [1:0] remap_mode; // From erx_cfg of erx_cfg.v
wire [11:0] remap_pattern; // From erx_cfg of erx_cfg.v
wire [11:0] remap_sel; // From erx_cfg of erx_cfg.v
wire test_mode; // From erx_cfg of erx_cfg.v
// End of automatics
//regs
wire [8:0] gpio_datain; // To erx_cfg of erx_cfg.v
wire [15:0] rx_status;
wire rxwr_full;
wire rxrr_full;
wire rxrd_full;
wire rxrd_empty;
wire rxwr_empty;
wire rxrr_empty;
wire [103:0] edma_packet; // From edma of edma.v, ...
/**************************************************************/
/*ELINK PROTOCOL LOGIC */
/**************************************************************/
defparam erx_protocol.ID=ID;
erx_protocol erx_protocol (/*AUTOINST*/
// Outputs
.erx_test_access (erx_test_access),
.erx_test_data (erx_test_data[31:0]),
.erx_rdwr_access (erx_rdwr_access),
.erx_rr_access (erx_rr_access),
.erx_packet (erx_packet[PW-1:0]),
// Inputs
.clk (clk),
.test_mode (test_mode),
.rx_packet (rx_packet[PW-1:0]),
.rx_burst (rx_burst),
.rx_access (rx_access));
/**************************************************************/
/*ADDRESS REMPAPPING */
/**************************************************************/
/*erx_remap AUTO_TEMPLATE (
.emesh_\(.*\)_out (emesh_remap_\1[]),
//Inputs
.emesh_access_in (erx_rdwr_access),
.emesh_\(.*\)_in (erx_\1[]),
.mmu_en (ecfg_rx_mmu_enable),
.emesh_packet_hi_out (),
);
*/
defparam erx_remap.ID = ID;
erx_remap erx_remap (/*AUTOINST*/
// Outputs
.emesh_access_out(emesh_remap_access), // Templated
.emesh_packet_out(emesh_remap_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.emesh_access_in(erx_rdwr_access), // Templated
.emesh_packet_in(erx_packet[PW-1:0]), // Templated
.remap_mode (remap_mode[1:0]),
.remap_sel (remap_sel[11:0]),
.remap_pattern (remap_pattern[11:0]),
.remap_base (remap_base[31:0]));
/************************************************************/
/*ELINK MEMORY MANAGEMENT UNIT */
/************************************************************/
/*emmu AUTO_TEMPLATE (
.emesh_\(.*\)_out (emmu_\1[]),
//Inputs
.emesh_\(.*\)_in (emesh_remap_\1[]),
.mmu_en (mmu_enable),
.rd_clk (clk),
.wr_clk (clk),
.mi_dout (mi_mmu_dout[DW-1:0]),
.emesh_packet_hi_out (),
.mi_en (mi_mmu_en),
);
*/
emmu erx_mmu (.mmu_bp (1'b0), //why is this zero??
.emesh_wait (1'b0),
/*AUTOINST*/
// Outputs
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
.emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
.emesh_packet_hi_out (), // Templated
// Inputs
.rd_clk (clk), // Templated
.wr_clk (clk), // Templated
.mmu_en (mmu_enable), // Templated
.mi_en (mi_mmu_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[DW-1:0]),
.emesh_access_in (emesh_remap_access), // Templated
.emesh_packet_in (emesh_remap_packet[PW-1:0])); // Templated
/************************************************************/
/*EMAILBOX */
/************************************************************/
/*emailbox AUTO_TEMPLATE (
.mi_en (mi_cfg_en),
.mi_dout (mi_mailbox_dout[]),
.wr_clk (clk),
.rd_clk (clk),
.emesh_access (emmu_access),
.emesh_packet (emmu_packet[PW-1:0]),
.rd_reset (reset),
.wr_reset (reset),
);
*/
defparam erx_mailbox.ID=ID;
emailbox erx_mailbox(
/*AUTOINST*/
// Outputs
.mi_dout (mi_mailbox_dout[63:0]), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
// Inputs
.wr_reset (reset), // Templated
.wr_clk (clk), // Templated
.rd_clk (clk), // Templated
.rd_reset (reset), // Templated
.emesh_access (emmu_access), // Templated
.emesh_packet (emmu_packet[PW-1:0]), // Templated
.mi_en (mi_cfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]),
.mi_din (mi_din[63:0]));
/************************************************************/
/* CONFIGURATION INTERFACE */
/************************************************************/
/*ecfg_if AUTO_TEMPLATE (
.wait_in (erx_cfg_wait),
.\(.*\)_in (erx_cfg_\1[]),
.\(.*\)_out (ecfg_\1[]),
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}),
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
.mi_dout3 (mi_mailbox_dout[63:0]),
);
*/
defparam erx_cfgif.RX=1;
ecfg_if erx_cfgif (/*AUTOINST*/
// Outputs
.mi_mmu_en (mi_mmu_en),
.mi_dma_en (mi_dma_en),
.mi_cfg_en (mi_cfg_en),
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[63:0]),
.access_out (ecfg_access), // Templated
.packet_out (ecfg_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.access_in (erx_cfg_access), // Templated
.packet_in (erx_cfg_packet[PW-1:0]), // Templated
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
.mi_dout3 (mi_mailbox_dout[63:0]), // Templated
.wait_in (erx_cfg_wait)); // Templated
/************************************************************/
/* ERX CONFIGURATION */
/************************************************************/
/*erx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
.mi_en (mi_cfg_en),
);
*/
assign rx_status[15:0] = {16'b0};
assign gpio_datain[8:0]=9'b0;
/*
assign gpio_datain[8:0]= {rx_frame_par[0],
rx_data_par[7],
rx_data_par[6],
rx_data_par[5],
rx_data_par[4],
rx_data_par[3],
rx_data_par[2],
rx_data_par[1],
rx_data_par[0]
};
*/
erx_cfg erx_cfg (.rx_status (rx_status[15:0]),
.timer_cfg (),
.rx_enable (),//TODO:what to do with this??
/*AUTOINST*/
// Outputs
.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
.mmu_enable (mmu_enable),
.remap_mode (remap_mode[1:0]),
.remap_base (remap_base[31:0]),
.remap_pattern (remap_pattern[11:0]),
.remap_sel (remap_sel[11:0]),
.idelay_value (idelay_value[44:0]),
.load_taps (load_taps),
.test_mode (test_mode),
// Inputs
.reset (reset),
.clk (clk),
.mi_en (mi_cfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[31:0]),
.erx_test_access (erx_test_access),
.erx_test_data (erx_test_data[31:0]),
.gpio_datain (gpio_datain[8:0]));
/************************************************************/
/*ELINK DMA */
/************************************************************/
/*edma AUTO_TEMPLATE (
.mi_en (mi_dma_en),
.edma_access (edma_access),
.mi_dout (mi_dma_dout[DW-1:0]),
);
*/
edma erx_dma(/*AUTOINST*/
// Outputs
.mi_dout (mi_dma_dout[DW-1:0]), // Templated
.edma_access (edma_access), // Templated
.edma_packet (edma_packet[PW-1:0]),
// Inputs
.reset (reset),
.clk (clk),
.mi_en (mi_dma_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]),
.mi_din (mi_din[63:0]),
.edma_wait (edma_wait));
/************************************************************/
/*ELINK RECEIVE DISTRIBUTOR ("DEMUX") */
/*(figures out who RX transaction belongs to) */
/************************************************************/
/*erx_arbiter AUTO_TEMPLATE (
//Inputs
.mmu_en (ecfg_rx_mmu_enable),
.ecfg_wait (erx_cfg_wait),
)
*/
defparam erx_arbiter.ID = ID;
erx_arbiter erx_arbiter (.timeout (1'b0),//TODO
/*AUTOINST*/
// Outputs
.rx_rd_wait (rx_rd_wait),
.rx_wr_wait (rx_wr_wait),
.edma_wait (edma_wait),
.ecfg_wait (erx_cfg_wait), // Templated
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
// Inputs
.erx_rr_access (erx_rr_access),
.erx_packet (erx_packet[PW-1:0]),
.emmu_access (emmu_access),
.emmu_packet (emmu_packet[PW-1:0]),
.edma_access (edma_access),
.edma_packet (edma_packet[PW-1:0]),
.ecfg_access (ecfg_access),
.ecfg_packet (ecfg_packet[PW-1:0]),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait));
endmodule // erx_core
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

156
parallella/fpga/parallella_base/parallella_base/src/erx_fifo.v
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@ -1,156 +0,0 @@
module erx_fifo (/*AUTOARG*/
// Outputs
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
rxrr_packet, rxrd_fifo_wait, rxrr_fifo_wait, rxwr_fifo_wait,
// Inputs
erx_reset, sys_reset, rx_lclk_div4, sys_clk, rxwr_wait, rxrd_wait,
rxrr_wait, rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access,
rxrr_fifo_packet, rxwr_fifo_access, rxwr_fifo_packet
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h800;
//reset & clocks
input erx_reset;
input sys_reset;
input rx_lclk_div4;
input sys_clk;
//WR to AXI master
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//RD to AXI master
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//RR to AXI slave
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//RD from IO
input rxrd_fifo_access; // To rxrd_fifo of fifo_cdc.v
input [PW-1:0] rxrd_fifo_packet; // To rxrd_fifo of fifo_cdc.v
output rxrd_fifo_wait; // From rxrd_fifo of fifo_cdc.v
//RR from IO
input rxrr_fifo_access; // To rxrr_fifo of fifo_cdc.v
input [PW-1:0] rxrr_fifo_packet; // To rxrr_fifo of fifo_cdc.v
output rxrr_fifo_wait; // From rxrr_fifo of fifo_cdc.v
//WR from IO
input rxwr_fifo_access; // To rxwr_fifo of fifo_cdc.v
input [PW-1:0] rxwr_fifo_packet; // To rxwr_fifo of fifo_cdc.v
output rxwr_fifo_wait; // From rxwr_fifo of fifo_cdc.v
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
/************************************************************/
/*FIFOs */
/*(for AXI 1. read request, 2. write, and 3. read response) */
/************************************************************/
/*fifo_cdc AUTO_TEMPLATE (
// Outputs
.packet_out (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
.access_out (@"(substring vl-cell-name 0 4)"_access),
.wait_out (@"(substring vl-cell-name 0 4)"_fifo_wait),
// Inputs
.clk_out (sys_clk),
.clk_in (rx_lclk_div4),
.access_in (@"(substring vl-cell-name 0 4)"_fifo_access),
.wait_in (@"(substring vl-cell-name 0 4)"_wait),
.reset_in (erx_reset),
.reset_out (sys_reset),
.packet_in (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
);
*/
//Read request fifo (from Epiphany)
fifo_cdc #(.DW(104), .DEPTH(32))
rxrd_fifo (
/*AUTOINST*/
// Outputs
.wait_out (rxrd_fifo_wait), // Templated
.access_out (rxrd_access), // Templated
.packet_out (rxrd_packet[PW-1:0]), // Templated
// Inputs
.clk_in (rx_lclk_div4), // Templated
.reset_in (erx_reset), // Templated
.access_in (rxrd_fifo_access), // Templated
.packet_in (rxrd_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.reset_out (sys_reset), // Templated
.wait_in (rxrd_wait)); // Templated
//Write fifo (from Epiphany)
fifo_cdc #(.DW(104), .DEPTH(32))
rxwr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (rxwr_fifo_wait), // Templated
.access_out (rxwr_access), // Templated
.packet_out (rxwr_packet[PW-1:0]), // Templated
// Inputs
.clk_in (rx_lclk_div4), // Templated
.reset_in (erx_reset), // Templated
.access_in (rxwr_fifo_access), // Templated
.packet_in (rxwr_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.reset_out (sys_reset), // Templated
.wait_in (rxwr_wait)); // Templated
//Read response fifo (for host)
fifo_cdc #(.DW(104), .DEPTH(32))
rxrr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (rxrr_fifo_wait), // Templated
.access_out (rxrr_access), // Templated
.packet_out (rxrr_packet[PW-1:0]), // Templated
// Inputs
.clk_in (rx_lclk_div4), // Templated
.reset_in (erx_reset), // Templated
.access_in (rxrr_fifo_access), // Templated
.packet_in (rxrr_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.reset_out (sys_reset), // Templated
.wait_in (rxrr_wait)); // Templated
endmodule // erx
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

356
parallella/fpga/parallella_base/parallella_base/src/erx_io.v
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@ -1,356 +0,0 @@
/*
This block receives the IO transaction and converts to a 104 bit packet.
*/
module erx_io (/*AUTOARG*/
// Outputs
rx_clkin, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
// Inputs
erx_io_reset, rx_lclk, rx_lclk_div4, idelay_value, load_taps,
rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
rxi_data_n, rx_wr_wait, rx_rd_wait
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
//#########################
//# reset, clocks
//#########################
input erx_io_reset; // high sped reset
input rx_lclk; // fast I/O clock
input rx_lclk_div4; // slow clock
output rx_clkin; // clock output for pll
//#########################
//# idelays
//#########################
input [44:0] idelay_value;
input load_taps;
//##########################
//# elink pins
//##########################
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
//##########################
//# erx logic interface
//##########################
output rx_access;
output rx_burst;
output [PW-1:0] rx_packet;
input rx_wr_wait;
input rx_rd_wait;
//############
//# WIRES
//############
wire [7:0] rxi_data;
wire rxi_frame;
wire rxi_lclk;
wire access_wide;
reg valid_packet;
wire [15:0] rx_word;
reg [15:0] rx_word_sync;
//############
//# REGS
//############
reg [7:0] data_even_reg;
reg [7:0] data_odd_reg;
wire rx_frame;
reg [111:0] rx_sample;
reg [6:0] rx_pointer;
reg access;
reg burst;
reg [PW-1:0] rx_packet_lclk;
reg rx_access;
reg [PW-1:0] rx_packet;
reg rx_burst;
wire rx_lclk_iddr;
wire [8:0] rxi_delay_in;
wire [8:0] rxi_delay_out;
reg reset_sync;
reg burst_detect;
//#####################
//#CREATE 112 BIT PACKET
//#####################
//write Pointer
always @ (posedge rx_lclk or posedge erx_io_reset)
if(erx_io_reset)
rx_pointer[6:0] <= 7'b0;
else if (~rx_frame)
rx_pointer[6:0] <= 7'b0000001; //new frame
else if (rx_pointer[6])
rx_pointer[6:0] <= 7'b0001000; //anticipate burst
else if(rx_frame)
rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
//convert to 112 bit packet
always @ (posedge rx_lclk)
if(rx_frame)
begin
if(rx_pointer[0])
rx_sample[15:0] <= rx_word[15:0];
if(rx_pointer[1])
rx_sample[31:16] <= rx_word[15:0];
if(rx_pointer[2])
rx_sample[47:32] <= rx_word[15:0];
if(rx_pointer[3])
rx_sample[63:48] <= rx_word[15:0];
if(rx_pointer[4])
rx_sample[79:64] <= rx_word[15:0];
if(rx_pointer[5])
rx_sample[95:80] <= rx_word[15:0];
if(rx_pointer[6])
rx_sample[111:96] <= rx_word[15:0];
end // if (rx_frame)
//#####################
//#DATA VALID SIGNAL
//####################
always @ (posedge rx_lclk)
begin
access <= rx_pointer[6];
valid_packet <= access;//data pipeline
end
always @ (posedge rx_lclk or posedge erx_io_reset)
if(erx_io_reset)
burst_detect <= 1'b0;
else if(access & rx_frame)
burst_detect <= 1'b1;
else if(~rx_frame)
burst_detect <= 1'b0;
//###################################
//#SAMPLE AND HOLD DATA
//###################################
//(..and shuffle data for 104 bit packet)
always @ (posedge rx_lclk)
if(access)
begin
//pipelin burst (delay by one frame)
burst <= burst_detect;
//access
rx_packet_lclk[0] <= rx_sample[40];
//write
rx_packet_lclk[1] <= rx_sample[41];
//datamode
rx_packet_lclk[3:2] <= rx_sample[43:42];
//ctrlmode
rx_packet_lclk[7:4] <= rx_sample[15:12];
//dstaddr
rx_packet_lclk[39:8] <= {rx_sample[11:8],
rx_sample[23:16],
rx_sample[31:24],
rx_sample[39:32],
rx_sample[47:44]};
//data
rx_packet_lclk[71:40] <= {rx_sample[55:48],
rx_sample[63:56],
rx_sample[71:64],
rx_sample[79:72]};
//srcaddr
rx_packet_lclk[103:72]<= {rx_sample[87:80],
rx_sample[95:88],
rx_sample[103:96],
rx_sample[111:104]
};
end
//###################################
//#SYNCHRONIZE TO SLOW CLK
//###################################
//stretch access pulse to 4 cycles
pulse_stretcher #(.DW(3))
ps0 (
.out(access_wide),
.in(valid_packet),
.clk(rx_lclk));
always @ (posedge rx_lclk_div4)
rx_access <= access_wide;
always @ (posedge rx_lclk_div4)
if(access_wide)
begin
rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
rx_burst <= burst;
end
//################################
//# I/O Buffers Instantiation
//################################
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_data[7:0]
(.I (rxi_data_p[7:0]),
.IB (rxi_data_n[7:0]),
.O (rxi_data[7:0]));
IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTD_ELINK))
ibuf_frame
(.I (rxi_frame_p),
.IB (rxi_frame_n),
.O (rxi_frame));
IBUFGDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_lclk (.I (rxi_lclk_p),
.IB (rxi_lclk_n),
.O (rx_clkin)
);
generate
if(ETYPE==1)
begin
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_wrwait (
.O(rxo_wr_wait_p),
.T(rx_wr_wait),
.I(1'b0)
);
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_rdwait (
.O(rxo_rd_wait_p),
.T(rx_rd_wait),
.I(1'b0)
);
assign rxo_wr_wait_n = 1'b0;
assign rxo_rd_wait_n = 1'b0;
end
else if(ETYPE==0)
begin
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_wrwait (
.O(rxo_wr_wait_p),
.OB(rxo_wr_wait_n),
.I(rx_wr_wait)
);
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_rdwait (.O(rxo_rd_wait_p),
.OB(rxo_rd_wait_n),
.I(rx_rd_wait)
);
end
endgenerate
//###################################
//#RX CLOCK for IDDR
//###################################
BUFIO i_rx_lclk_iddr (.I(rx_clkin), .O(rx_lclk_iddr));//for iddr
//###################################
//#IDELAY CIRCUIT
//###################################
assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
genvar j;
generate for(j=0; j<9; j=j+1)
begin : gen_idelay
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.IDELAY_TYPE("VAR_LOAD"),
.IDELAY_VALUE(5'b0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.C(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CINVCTRL(1'b0), // inverts clock polarity
.CNTVALUEIN(idelay_value[(j+1)*5-1:j*5]), //variable tap
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LD(load_taps), // load new
.LDPIPEEN(1'b0), // only for pipeline mode
.REGRST(1'b0) // only for pipeline mode
);
end // block: gen_idelay
endgenerate
//#############################
//# IDDR SAMPLERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_iddr
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_data (
.Q1 (rx_word[i]),
.Q2 (rx_word[i+8]),
.C (rx_lclk_iddr),
.CE (1'b1),
.D (rxi_delay_out[i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_frame (
.Q1 (rx_frame),
.Q2 (),
.C (rx_lclk_iddr),
.CE (1'b1),
.D (rxi_delay_out[8]),
.R (1'b0),
.S (1'b0)
);
endmodule // erx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

113
parallella/fpga/parallella_base/parallella_base/src/erx_protocol.v
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@ -1,113 +0,0 @@
/*
This block handles the autoincrement needed for bursting and detects
read responses
*/
`include "elink_regmap.v"
module erx_protocol (/*AUTOARG*/
// Outputs
erx_test_access, erx_test_data, erx_rdwr_access, erx_rr_access,
erx_packet,
// Inputs
clk, test_mode, rx_packet, rx_burst, rx_access
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h800; //link id
// System reset input
input clk;
//test mode
input test_mode; //block all traffic in test mode
output erx_test_access;
output [31:0] erx_test_data;
// Parallel interface, 8 eLink bytes at a time
input [PW-1:0] rx_packet;
input rx_burst;
input rx_access;
// Output to MMU / filter
output erx_rdwr_access;
output erx_rr_access;
output [PW-1:0] erx_packet;
//wires
reg [31:0] dstaddr_reg;
wire [31:0] dstaddr_next;
wire [31:0] dstaddr_mux;
reg erx_rdwr_access;
reg erx_rr_access;
reg [PW-1:0] erx_packet;
wire [11:0] myid;
wire [31:0] rx_addr;
wire read_response;
reg erx_test_access;
//parsing inputs
assign myid[11:0] = ID;
assign rx_addr[31:0] = rx_packet[39:8];
//Address generator for bursting
always @ (posedge clk)
if(rx_access)
dstaddr_reg[31:0] <= dstaddr_mux[31:0];
assign dstaddr_next[31:0] = dstaddr_reg[31:0] + 4'b1000;
assign dstaddr_mux[31:0] = rx_burst ? dstaddr_next[31:0] :
rx_addr[31:0];
//Read response detector
assign read_response = (rx_addr[31:20] == myid[11:0]) &
(rx_addr[19:16] == `EGROUP_RR);
//Pipeline stage and decode
always @ (posedge clk)
begin
//Write/read request
erx_rdwr_access <= ~test_mode & rx_access & ~read_response;
//Read response
erx_rr_access <= ~test_mode & rx_access & read_response;
//Test packet
erx_test_access <= test_mode & rx_access & ~read_response;
//Common packet
erx_packet[PW-1:0] <= {rx_packet[PW-1:40],
dstaddr_mux[31:0],
{1'b0,rx_packet[7:1]} //NOTE: remvoing redundant access packet bit
}; //This is to conform to new format
end
//Testdata to write
assign erx_test_data[31:0] = erx_packet[71:40];
endmodule // erx_protocol
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

82
parallella/fpga/parallella_base/parallella_base/src/erx_remap.v
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@ -1,82 +0,0 @@
module erx_remap (/*AUTOARG*/
// Outputs
emesh_access_out, emesh_packet_out,
// Inputs
clk, emesh_access_in, emesh_packet_in, remap_mode, remap_sel,
remap_pattern, remap_base
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h808;
//Clock/reset
input clk;
//Input from arbiter
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
//Configuration
input [1:0] remap_mode; //00=none,01=static,02=continuity
input [11:0] remap_sel; //number of bits to remap
input [11:0] remap_pattern; //static pattern to map to
input [31:0] remap_base; //remap offset
//Output to TX IO
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
wire [31:0] static_remap;
wire [31:0] dynamic_remap;
wire [31:0] remap_mux;
wire write_in;
wire read_in;
wire [31:0] addr_in;
wire [31:0] addr_out;
wire remap_en;
reg emesh_access_out;
reg [PW-1:0] emesh_packet_out;
//TODO:FIX!??
parameter[5:0] colid = ID[5:0];
//parsing packet
assign addr_in[31:0] = emesh_packet_in[39:8];
assign write_in = emesh_packet_in[1];
assign read_in = ~emesh_packet_in[1];
//simple static remap
assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
(~remap_sel[11:0] & addr_in[31:20]);
assign static_remap[19:0] = addr_in[19:0];
//more complex compresssed map
assign dynamic_remap[31:0] = addr_in[31:0] //input
- (colid << 20) //subtracing elink (start at 0)
+ remap_base[31:0] //adding back base
- (addr_in[31:26]<<$clog2(colid));
//Static, dynamic, or no remap
assign remap_mux[31:0] = (remap_mode[1:0]==2'b00) ? addr_in[31:0] :
(remap_mode[1:0]==2'b01) ? static_remap[31:0] :
dynamic_remap[31:0];
//Access pipeline
always @ (posedge clk)
emesh_access_out <= emesh_access_in;
//Packet Remapping
always @ (posedge clk)
emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
remap_mux[31:0],
emesh_packet_in[7:0]
};
endmodule // etx_mux

503
parallella/fpga/parallella_base/parallella_base/src/esaxi.v
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`include "elink_regmap.v"
module esaxi (/*autoarg*/
// Outputs
txwr_access, txwr_packet, txrd_access, txrd_packet, rxrr_wait,
s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
s_axi_wready,
// Inputs
txwr_wait, txrd_wait, rxrr_access, rxrr_packet, s_axi_aclk,
s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
s_axi_wstrb, s_axi_wvalid
);
parameter [11:0] ID = 12'h810;
parameter S_IDW = 12;
parameter PW = 104;
parameter [15:0] RETURN_ADDR = {ID,`EGROUP_RR};
parameter AW = 32;
parameter DW = 32;
/*****************************/
/*Write request for TX fifo */
/*****************************/
output txwr_access;
output [PW-1:0] txwr_packet;
input txwr_wait;
/*****************************/
/*Read request for TX fifo */
/*****************************/
output txrd_access;
output [PW-1:0] txrd_packet;
input txrd_wait;
/*****************************/
/*Read response from RX fifo */
/*****************************/
input rxrr_access;
input [PW-1:0] rxrr_packet;
output rxrr_wait;
/*****************************/
/*AXI slave interface */
/*****************************/
//Clock and reset
input s_axi_aclk;
input s_axi_aresetn;
//Read address channel
input [S_IDW-1:0] s_axi_arid; //write address ID
input [31:0] s_axi_araddr;
input [1:0] s_axi_arburst;
input [3:0] s_axi_arcache;
input [1:0] s_axi_arlock;
input [7:0] s_axi_arlen;
input [2:0] s_axi_arprot;
input [3:0] s_axi_arqos;
output s_axi_arready;
input [2:0] s_axi_arsize;
input s_axi_arvalid;
//Write address channel
input [S_IDW-1:0] s_axi_awid; //write address ID
input [31:0] s_axi_awaddr;
input [1:0] s_axi_awburst;
input [3:0] s_axi_awcache;
input [1:0] s_axi_awlock;
input [7:0] s_axi_awlen;
input [2:0] s_axi_awprot;
input [3:0] s_axi_awqos;
input [2:0] s_axi_awsize;
input s_axi_awvalid;
output s_axi_awready;
//Buffered write response channel
output [S_IDW-1:0] s_axi_bid; //write address ID
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
//Read channel
output [S_IDW-1:0] s_axi_rid; //write address ID
output [31:0] s_axi_rdata;
output s_axi_rlast;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
//Write channel
input [S_IDW-1:0] s_axi_wid; //write address ID
input [31:0] s_axi_wdata;
input s_axi_wlast;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
//###################################################
//#WIRE/REG DECLARATIONS
//###################################################
reg s_axi_awready;
reg s_axi_wready;
reg s_axi_bvalid;
reg [1:0] s_axi_bresp;
reg s_axi_arready;
reg [31:0] axi_awaddr; // 32b for epiphany addr
reg [1:0] axi_awburst;
reg [2:0] axi_awsize;
reg [S_IDW-1:0] axi_bid; //what to do with this?
reg [31:0] axi_araddr;
reg [7:0] axi_arlen;
reg [1:0] axi_arburst;
reg [2:0] axi_arsize;
reg [31:0] s_axi_rdata;
reg [1:0] s_axi_rresp;
reg s_axi_rlast;
reg s_axi_rvalid;
reg [S_IDW-1:0] s_axi_rid;
reg read_active;
reg [31:0] read_addr;
reg write_active;
reg b_wait; // waiting to issue write response (unlikely?)
reg txwr_access;
reg [1:0] txwr_datamode;
reg [31:0] txwr_dstaddr;
reg [31:0] txwr_data;
reg [31:0] txwr_data_reg;
reg [31:0] txwr_dstaddr_reg;
reg [1:0] txwr_datamode_reg;
reg txrd_access;
reg [1:0] txrd_datamode;
reg [31:0] txrd_dstaddr;
reg [31:0] txrd_srcaddr; //read reaspne address
reg pre_wr_en; // delay for data alignment
reg ractive_reg; // need leading edge of active for 1st req
reg rnext;
wire last_wr_beat;
wire last_rd_beat;
wire [31:0] rxrr_mux_data;
wire [DW-1:0] rxrr_data;
//###################################################
//#PACKET TO MESH
//###################################################
//TXWR
emesh2packet e2p_txwr (
// Outputs
.packet_out (txwr_packet[PW-1:0]),
// Inputs
.write_in (1'b1),
.datamode_in (txwr_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txwr_dstaddr[AW-1:0]),
.data_in (txwr_data[DW-1:0]),
.srcaddr_in (32'b0)//only 32b slave write supported
);
//TXRD
emesh2packet e2p_txrd (
// Outputs
.packet_out (txrd_packet[PW-1:0]),
// Inputs
.write_in (txrd_write),
.datamode_in (txrd_datamode[1:0]),
.ctrlmode_in (4'b0),
.dstaddr_in (txrd_dstaddr[AW-1:0]),
.data_in (32'b0),
.srcaddr_in (txrd_srcaddr[AW-1:0])
);
//RXRR
packet2emesh p2e_rxrr (
// Outputs
.write_out (),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (),
.data_out (rxrr_data[DW-1:0]),
.srcaddr_out (),
// Inputs
.packet_in (rxrr_packet[PW-1:0])
);
//###################################################
//#WRITE ADDRESS CHANNEL
//###################################################
assign last_wr_beat = s_axi_wready & s_axi_wvalid & s_axi_wlast;
// axi_awready is asserted when there is no write transfer in progress
always @(posedge s_axi_aclk )
begin
if(~s_axi_aresetn)
begin
s_axi_awready <= 1'b1; //TODO: why not set default as 1?
write_active <= 1'b0;
end
else
begin
// we're always ready for an address cycle if we're not doing something else
// note: might make this faster by going ready on last beat instead of after,
// but if we want the very best each channel should be fifo'd.
if( ~s_axi_awready & ~write_active & ~b_wait )
s_axi_awready <= 1'b1;
else if( s_axi_awvalid )
s_axi_awready <= 1'b0;
// the write cycle is "active" as soon as we capture an address, it
// ends on the last beat.
if( s_axi_awready & s_axi_awvalid )
write_active <= 1'b1;
else if( last_wr_beat )
write_active <= 1'b0;
end // else: !if(~s_axi_aresetn)
end // always @ (posedge s_axi_aclk )
// capture address & other aw info, update address during cycle
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
axi_bid[S_IDW-1:0] <= 'd0; // capture for write response
axi_awaddr[31:0] <= 32'd0;
axi_awsize[2:0] <= 3'd0;
axi_awburst[1:0] <= 2'd0;
end
else
begin
if( s_axi_awready & s_axi_awvalid )
begin
axi_bid[S_IDW-1:0] <= s_axi_awid[S_IDW-1:0];
axi_awaddr[31:0] <= s_axi_awaddr[31:0];
axi_awsize[2:0] <= s_axi_awsize[2:0]; // 0=byte, 1=16b, 2=32b
axi_awburst[1:0] <= s_axi_awburst[1:0]; // type, 0=fixed, 1=incr, 2=wrap
end
else if( s_axi_wvalid & s_axi_wready )
if( axi_awburst == 2'b01 )
begin //incremental burst
// the write address for all the beats in the transaction are increments by the data width.
// note: this should be based on awsize instead to support narrow bursts, i think.
axi_awaddr[31:2] <= axi_awaddr[31:2] + 30'd1;
//awaddr alignedto data width
axi_awaddr[1:0] <= 2'b0;
end // both fixed & wrapping types are treated as fixed, no update.
end // else: !if(~s_axi_aresetn)
//###################################################
//#WRITE RESPONSE CHANNEL
//###################################################
assign s_axi_bid = axi_bid;
always @ (posedge s_axi_aclk)
if(~s_axi_aresetn)
s_axi_wready <= 1'b0;
else
begin
if( last_wr_beat )
s_axi_wready <= 1'b0;
else if( write_active )
s_axi_wready <= ~txwr_wait;
end
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_bvalid <= 1'b0;
s_axi_bresp[1:0] <= 2'b0;
b_wait <= 1'b0;
end
else
begin
if( last_wr_beat )
begin
s_axi_bvalid <= 1'b1;
s_axi_bresp[1:0] <= 2'b0; // 'okay' response
b_wait <= ~s_axi_bready; // note: assumes bready will not drop without valid?
end
else if (s_axi_bready & s_axi_bvalid)
begin
s_axi_bvalid <= 1'b0;
b_wait <= 1'b0;
end
end // else: !if( s_axi_aresetn == 1'b0 )
//###################################################
//#READ REQUEST CHANNEL
//###################################################
assign last_rd_beat = s_axi_rvalid & s_axi_rlast & s_axi_rready;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
s_axi_arready <= 1'b0;
read_active <= 1'b0;
end
else
begin
//arready
if( ~s_axi_arready & ~read_active )
s_axi_arready <= 1'b1;
else if( s_axi_arvalid )
s_axi_arready <= 1'b0;
//read_active
if( s_axi_arready & s_axi_arvalid )
read_active <= 1'b1;
else if( last_rd_beat )
read_active <= 1'b0;
end // else: !if( s_axi_aresetn == 1'b0 )
//Read address channel state machine
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
axi_araddr[31:0] <= 0;
axi_arlen <= 8'd0;
axi_arburst <= 2'd0;
axi_arsize[2:0] <= 3'b0;
s_axi_rlast <= 1'b0;
s_axi_rid[S_IDW-1:0] <= 'd0;
end
else
begin
if( s_axi_arready & s_axi_arvalid )
begin
axi_araddr[31:0] <= s_axi_araddr[31:0]; //NOTE: upper 2 bits get chopped by Zynq
axi_arlen[7:0] <= s_axi_arlen[7:0];
axi_arburst <= s_axi_arburst;
axi_arsize <= s_axi_arsize;
s_axi_rlast <= ~(|s_axi_arlen[7:0]);
s_axi_rid[S_IDW-1:0] <= s_axi_arid[S_IDW-1:0];
end
else if( s_axi_rvalid & s_axi_rready)
begin
axi_arlen[7:0] <= axi_arlen[7:0] - 1;
if(axi_arlen[7:0] == 8'd1)
s_axi_rlast <= 1'b1;
if( s_axi_arburst == 2'b01)
begin //incremental burst
// the read address for all the beats in the transaction are increments by awsize
// note: this should be based on awsize instead to support narrow bursts, i think?
axi_araddr[31:2] <= axi_araddr[31:2] + 1;//TODO: doesn;t seem right...
//araddr aligned to 4 byte boundary
axi_araddr[1:0] <= 2'b0;
//for awsize = 4 bytes (010)
end
end // if ( s_axi_rvalid & s_axi_rready)
end // else: !if( s_axi_aresetn == 1'b0 )
//###################################################
//#WRITE REQUEST
//###################################################
assign txwr_write = 1'b1;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
txwr_data_reg[31:0] <= 32'd0;
txwr_dstaddr_reg[31:0] <= 32'd0;
txwr_datamode_reg[1:0] <= 2'd0;
txwr_access <= 1'b0;
pre_wr_en <= 1'b0;
end
else
begin
pre_wr_en <= s_axi_wready & s_axi_wvalid;
txwr_access <= pre_wr_en;
txwr_datamode_reg[1:0] <= axi_awsize[1:0];
txwr_dstaddr_reg[31:2] <= axi_awaddr[31:2]; //set lsbs of address based on write strobes
if(s_axi_wstrb[0] | (axi_awsize[1:0]==2'b10))
begin
txwr_data_reg[31:0] <= s_axi_wdata[31:0];
txwr_dstaddr_reg[1:0] <= 2'd0;
end
else if(s_axi_wstrb[1])
begin
txwr_data_reg[31:0] <= {8'd0, s_axi_wdata[31:8]};
txwr_dstaddr_reg[1:0] <= 2'd1;
end
else if(s_axi_wstrb[2])
begin
txwr_data_reg[31:0] <= {16'd0, s_axi_wdata[31:16]};
txwr_dstaddr_reg[1:0] <= 2'd2;
end
else
begin
txwr_data_reg[31:0] <= {24'd0, s_axi_wdata[31:24]};
txwr_dstaddr_reg[1:0] <= 2'd3;
end
end // else: !if(~s_axi_aresetn)
//Pipeline stage!
always @( posedge s_axi_aclk )
begin
txwr_data[31:0] <= txwr_data_reg[31:0];
txwr_dstaddr[31:0] <= txwr_dstaddr_reg[31:0];
txwr_datamode[1:0] <= txwr_datamode_reg[1:0];
end
//###################################################
//#READ REQUEST (DATA CHANNEL)
//###################################################
// -- reads are performed by sending a read
// -- request out the tx port and waiting for
// -- data to come back through the rx read response port.
// --
// -- because elink reads are not generally
// -- returned in order, we will only allow
// -- one at a time.
//TODO: Fix this nonsense, need to improve performance
//Allow up to N outstanding transactions, use ID to match them up
//Need to look at txrd_wait signal
assign txrd_write = 1'b0;
always @( posedge s_axi_aclk )
if (~s_axi_aresetn)
begin
txrd_access <= 1'b0;
txrd_datamode[1:0] <= 2'd0;
txrd_dstaddr[31:0] <= 32'd0;
txrd_srcaddr[31:0] <= 32'd0;
ractive_reg <= 1'b0;
rnext <= 1'b0;
end
else
begin
ractive_reg <= read_active;
rnext <= s_axi_rvalid & s_axi_rready & ~s_axi_rlast;
txrd_access <= ( ~ractive_reg & read_active ) | rnext;
txrd_datamode[1:0] <= axi_arsize[1:0];
txrd_dstaddr[31:0] <= axi_araddr[31:0];
txrd_srcaddr[31:0] <= {RETURN_ADDR, 16'd0};
//TODO: use arid+srcaddr for out of order ?
end
//###################################################
//#READ RESPONSE (DATA CHANNEL)
//###################################################
//Read response AXI state machine
//Only one outstanding read
assign rxrr_wait = 1'b0;
always @( posedge s_axi_aclk )
if (!s_axi_aresetn)
begin
s_axi_rvalid <= 1'b0;
s_axi_rdata[31:0] <= 32'd0;
s_axi_rresp <= 2'd0;
end
else
begin
if( rxrr_access )
begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= 2'd0;
case( axi_arsize[1:0] )
2'b00: s_axi_rdata[31:0] <= {4{rxrr_data[7:0]}}; //8-bit
2'b01: s_axi_rdata[31:0] <= {2{rxrr_data[15:0]}}; //16-bit
default: s_axi_rdata[31:0] <= rxrr_data[31:0]; //32-bit
endcase // case ( axi_arsize[1:0] )
end
else if( s_axi_rready )
s_axi_rvalid <= 1'b0;
end // else: !if( s_axi_aresetn == 1'b0 )
endmodule // esaxi
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
Contributed by Fred Huettig <fred@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

234
parallella/fpga/parallella_base/parallella_base/src/etx.v
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@ -1,234 +0,0 @@
module etx(/*AUTOARG*/
// Outputs
tx_active, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
txo_data_p, txo_data_n, cclk_p, cclk_n, chip_resetb, txrd_wait,
txwr_wait, txrr_wait, etx_cfg_access, etx_cfg_packet, etx_reset,
tx_lclk_div4,
// Inputs
sys_clk, sys_reset, soft_reset, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, txrd_access, txrd_packet,
txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
//Reset and clocks
input sys_clk; // clock for fifos
input sys_reset; // reset for fifos
input soft_reset; // software controlled reset
output tx_active; // tx ready to transmit
//Transmit signals for IO
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
//Epiphany Chip Signals
output cclk_p,cclk_n;
output chip_resetb;
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
output etx_reset;
output tx_lclk_div4;
input etx_cfg_wait;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire tx_lclk; // From etx_clocks of etx_clocks.v
wire tx_lclk90; // From etx_clocks of etx_clocks.v
wire tx_lclk_io; // From etx_clocks of etx_clocks.v
// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire tx_access; // From etx_core of etx_core.v
wire tx_burst; // From etx_core of etx_core.v
wire tx_io_wait; // From etx_io of etx_io.v
wire [PW-1:0] tx_packet; // From etx_core of etx_core.v
wire tx_rd_wait; // From etx_io of etx_io.v
wire tx_wr_wait; // From etx_io of etx_io.v
wire txrd_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrd_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrd_fifo_wait; // From etx_core of etx_core.v
wire txrr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrr_fifo_wait; // From etx_core of etx_core.v
wire txwr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txwr_fifo_wait; // From etx_core of etx_core.v
/************************************************************/
/*Clocks */
/************************************************************/
etx_clocks etx_clocks (
.etx_io_reset (etx_io_reset),
/*AUTOINST*/
// Outputs
.tx_lclk (tx_lclk),
.tx_lclk_io (tx_lclk_io),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.etx_reset (etx_reset),
.chip_resetb (chip_resetb),
.tx_active (tx_active),
// Inputs
.sys_reset (sys_reset),
.soft_reset (soft_reset),
.sys_clk (sys_clk));
/************************************************************/
/*FIFOs */
/************************************************************/
etx_fifo etx_fifo (/*AUTOINST*/
// Outputs
.txrd_wait (txrd_wait),
.txwr_wait (txwr_wait),
.txrr_wait (txrr_wait),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.txrd_fifo_access (txrd_fifo_access),
.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
.txrr_fifo_access (txrr_fifo_access),
.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
.txwr_fifo_access (txwr_fifo_access),
.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
// Inputs
.etx_reset (etx_reset),
.sys_reset (sys_reset),
.sys_clk (sys_clk),
.tx_lclk_div4 (tx_lclk_div4),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait),
.txrd_fifo_wait (txrd_fifo_wait),
.txrr_fifo_wait (txrr_fifo_wait),
.txwr_fifo_wait (txwr_fifo_wait));
/***********************************************************/
/*ELINK CORE LOGIC */
/***********************************************************/
/*etx_core AUTO_TEMPLATE ( .tx_access (tx_access),
.tx_burst (tx_burst),
.tx_io_wait (tx_io_wait),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait),
.tx_packet (tx_packet[PW-1:0]),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait),
.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
.\(.*\)_access (\1_fifo_access),
.\(.*\)_wait (\1_fifo_wait),
);
*/
defparam etx_core.ID=ID;
etx_core etx_core (.clk (tx_lclk_div4),
.reset (etx_reset),
/*AUTOINST*/
// Outputs
.tx_access (tx_access), // Templated
.tx_burst (tx_burst), // Templated
.tx_packet (tx_packet[PW-1:0]), // Templated
.txrd_wait (txrd_fifo_wait), // Templated
.txrr_wait (txrr_fifo_wait), // Templated
.txwr_wait (txwr_fifo_wait), // Templated
.etx_cfg_access (etx_cfg_access), // Templated
.etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated
// Inputs
.tx_io_wait (tx_io_wait), // Templated
.tx_rd_wait (tx_rd_wait), // Templated
.tx_wr_wait (tx_wr_wait), // Templated
.txrd_access (txrd_fifo_access), // Templated
.txrd_packet (txrd_fifo_packet[PW-1:0]), // Templated
.txrr_access (txrr_fifo_access), // Templated
.txrr_packet (txrr_fifo_packet[PW-1:0]), // Templated
.txwr_access (txwr_fifo_access), // Templated
.txwr_packet (txwr_fifo_packet[PW-1:0]), // Templated
.etx_cfg_wait (etx_cfg_wait)); // Templated
/***********************************************************/
/*TRANSMIT I/O LOGIC */
/***********************************************************/
defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
etx_io etx_io (.reset (etx_io_reset),
/*AUTOINST*/
// Outputs
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.tx_io_wait (tx_io_wait),
.tx_wr_wait (tx_wr_wait),
.tx_rd_wait (tx_rd_wait),
// Inputs
.tx_lclk (tx_lclk),
.tx_lclk_io (tx_lclk_io),
.tx_lclk90 (tx_lclk90),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.tx_packet (tx_packet[PW-1:0]),
.tx_access (tx_access),
.tx_burst (tx_burst));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

191
parallella/fpga/parallella_base/parallella_base/src/etx_arbiter.v
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@ -1,191 +0,0 @@
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response)
and the DMA channel, arbitrates between the active channels, and forwards
the result to the transmit output pins.
Arbitration Priority:
1) host writes (highest)
2) read requests from host
3) read responses
*/
module etx_arbiter (/*AUTOARG*/
// Outputs
txwr_wait, txrd_wait, txrr_wait, etx_access, etx_packet, etx_rr,
// Inputs
clk, reset, txwr_access, txwr_packet, txrd_access, txrd_packet,
txrr_access, txrr_packet, etx_rd_wait, etx_wr_wait, etx_cfg_wait,
ctrlmode_bypass, ctrlmode
);
parameter PW = 104;
parameter ID = 0;
//tx clock and reset
input clk;
input reset;
//Write Request (from slave)
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Request (from slave)
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Read Response (from master)
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Wait signal inputs
input etx_rd_wait;
input etx_wr_wait;
input etx_cfg_wait;
//ctrlmode for rd/wr transactions
input ctrlmode_bypass;
input [3:0] ctrlmode;
//Transaction for IO protocol
output etx_access;
output [PW-1:0] etx_packet;
output etx_rr; //bypass translation on read response
//regs
reg etx_access;
reg [PW-1:0] etx_packet;
reg etx_rr; //bypass translation on read response
//wires
wire [3:0] txrd_ctrlmode;
wire [3:0] txwr_ctrlmode;
wire access_in;
wire [PW-1:0] etx_packet_mux;
wire txrr_grant;
wire txrd_grant;
wire txwr_grant;
wire txrr_arb_wait;
wire txrd_arb_wait;
wire txwr_arb_wait;
wire [PW-1:0] txrd_data;
wire [PW-1:0] txwr_data;
wire [PW-1:0] etx_mux;
wire write_in;
//##########################################################################
//# Insert special control mode in packet
//##########################################################################
assign txrd_ctrlmode[3:0] = ctrlmode_bypass ? ctrlmode[3:0] :
txrd_packet[6:3];
assign txwr_ctrlmode[3:0] = ctrlmode_bypass ? ctrlmode[3:0] :
txwr_packet[6:3];
assign txrd_data[PW-1:0] = {txrd_packet[PW-1:8],
txrd_ctrlmode[3:0],
txrd_packet[3:0]};
assign txwr_data[PW-1:0] = {txwr_packet[PW-1:8],
txwr_ctrlmode[3:0],
txwr_packet[3:0]};
//##########################################################################
//# Arbiter
//##########################################################################
arbiter_priority #(.ARW(3)) arbiter (.grant({txrr_grant,
txrd_grant,
txwr_grant //highest priority
}),
.await({txrr_arb_wait,
txrd_arb_wait,
txwr_arb_wait
}),
.request({txrr_access,
txrd_access,
txwr_access
})
);
//Priority Mux
assign etx_mux[PW-1:0] =({(PW){txwr_grant}} & txwr_data[PW-1:0]) |
({(PW){txrd_grant}} & txrd_data[PW-1:0]) |
({(PW){txrr_grant}} & txrr_packet[PW-1:0]);
//######################################################################
//Pushback (stall) Signals
//######################################################################
//Write waits on pin wr wait or cfg_wait
assign txwr_wait = etx_wr_wait |
etx_cfg_wait;
//Host read request (self throttling, one read at a time)
assign txrd_wait = etx_rd_wait |
etx_cfg_wait |
txrd_arb_wait;
//Read response
assign txrr_wait = etx_wr_wait |
etx_cfg_wait |
txrr_arb_wait;
//#####################################################################
//# Pipeline stage (arbiter+mux takes time..)
//#####################################################################
assign access_in = (txwr_grant & ~txwr_wait) |
(txrd_grant & ~txrd_wait) |
(txrr_grant & ~txrr_wait);
//Pipeline + stall
assign write_in = etx_mux[1];
//access
always @ (posedge clk)
if (reset)
begin
etx_access <= 1'b0;
etx_rr <= 1'b0;
end
else if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
begin
etx_access <= access_in;
etx_rr <= txrr_grant;
end
//packet
always @ (posedge clk)
if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
etx_packet[PW-1:0] <= etx_mux[PW-1:0];
endmodule // etx_arbiter
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

161
parallella/fpga/parallella_base/parallella_base/src/etx_cfg.v
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@ -1,161 +0,0 @@
/*
########################################################################
ELINK TX CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
module etx_cfg (/*AUTOARG*/
// Outputs
mi_dout, tx_enable, mmu_enable, gpio_enable, remap_enable,
gpio_data, ctrlmode, ctrlmode_bypass,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, tx_status
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter PW = 104;
parameter RFAW = 6;
parameter DEFAULT_VERSION = 16'h0000;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset;
input clk;
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr; // complete address (no shifting!)
input [31:0] mi_din; // (lower 2 bits not used)
output [31:0] mi_dout;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//tx (static configs)
output tx_enable; // enable signal for TX
output mmu_enable; // enables MMU on transmit path
output gpio_enable; // forces TX output pins to constants
output remap_enable; // enable address remapping
input [15:0] tx_status; // etx status signals
//sampled by tx_lclk (test)
output [8:0] gpio_data; // data for elink outputs (static)
//dynamic (control timing by use mode)
output [3:0] ctrlmode; // value for emesh ctrlmode tag
output ctrlmode_bypass; // selects ctrlmode
//registers
reg [15:0] ecfg_version_reg;
reg [10:0] ecfg_tx_config_reg;
reg [8:0] ecfg_tx_gpio_reg;
reg [2:0] ecfg_tx_status_reg;
reg [31:0] mi_dout;
reg ecfg_access;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_tx_config_write;
wire ecfg_tx_gpio_write;
wire ecfg_tx_test_write;
wire ecfg_tx_addr_write;
wire ecfg_tx_data_write;
wire loop_mode;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_version_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_VERSION);
assign ecfg_tx_config_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_CFG);
assign ecfg_tx_status_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_STATUS);
assign ecfg_tx_gpio_write = ecfg_write & (mi_addr[RFAW+1:2]==`ETX_GPIO);
//###########################
//# TX CONFIG
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_config_reg[10:0] <= 11'b0;
else if (ecfg_tx_config_write)
ecfg_tx_config_reg[10:0] <= mi_din[10:0];
assign tx_enable = 1'b1;//TODO: fix! ecfg_tx_config_reg[0];
assign mmu_enable = ecfg_tx_config_reg[1];
assign remap_enable = ecfg_tx_config_reg[3:2]==2'b01;
assign ctrlmode[3:0] = ecfg_tx_config_reg[7:4];
assign ctrlmode_bypass = ecfg_tx_config_reg[8];
assign gpio_enable = (ecfg_tx_config_reg[10:9]==2'b01);
//###########################
//# STATUS REGISTER
//###########################
always @ (posedge clk)
if(reset)
ecfg_tx_status_reg[2:0] <= 'd0;
else
ecfg_tx_status_reg[2:0]<= ecfg_tx_status_reg[2:0] | tx_status[2:0];
//###########################
//# GPIO DATA
//###########################
always @ (posedge clk)
if (ecfg_tx_gpio_write)
ecfg_tx_gpio_reg[8:0] <= mi_din[8:0];
assign gpio_data[8:0] = ecfg_tx_gpio_reg[8:0];
//###########################
//# VERSION
//###########################
always @ (posedge clk)
if(reset)
ecfg_version_reg[15:0] <= DEFAULT_VERSION;
else if (ecfg_version_write)
ecfg_version_reg[15:0] <= mi_din[15:0];
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(ecfg_read)
case(mi_addr[RFAW+1:2])
`ETX_CFG: mi_dout[31:0] <= {21'b0, ecfg_tx_config_reg[10:0]};
`ETX_GPIO: mi_dout[31:0] <= {23'b0, ecfg_tx_gpio_reg[8:0]};
`ETX_STATUS: mi_dout[31:0] <= {16'b0, tx_status[15:3],ecfg_tx_status_reg[2:0]};
`E_VERSION: mi_dout[31:0] <= {16'b0, ecfg_version_reg[15:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
mi_dout[31:0] <= 32'd0;
endmodule // ecfg_tx
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

302
parallella/fpga/parallella_base/parallella_base/src/etx_clocks.v
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@ -1,302 +0,0 @@
`include "elink_constants.v"
module etx_clocks (/*AUTOARG*/
// Outputs
tx_lclk, tx_lclk_io, tx_lclk90, tx_lclk_div4, cclk_p, cclk_n,
etx_reset, etx_io_reset, chip_resetb, tx_active,
// Inputs
sys_reset, soft_reset, sys_clk
);
`ifdef TARGET_SIMPLE
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_TXCLK = 300;
parameter FREQ_CCLK = 600;
parameter TXCLK_PHASE = 90; //txclk phase shift
//Don't touch these! (derived parameters)
localparam real SYSCLK_PERIOD = 1000.000000/FREQ_SYSCLK;
localparam integer TXCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_TXCLK;
localparam integer CCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_CCLK;
//VCO multiplers
parameter MMCM_VCO_MULT = 12; //TX + CCLK
//Input clock, reset, config interface
input sys_reset; // por reset (hw)
input soft_reset; // rx enable signal (sw)
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
//TX Clocks
output tx_lclk; // tx clock for IO state machine
output tx_lclk_io; // tx clock for DDR IO
output tx_lclk90; // tx output clock shifted by 90 degrees
output tx_lclk_div4; // tx slow clock for logic
//Epiphany "free running" clock
output cclk_p, cclk_n;
//Reset
output etx_reset; // reset for tx core logic
output etx_io_reset; // io reset (synced to high speed clock)
output chip_resetb; // reset fpr Epiphany chip
output tx_active; // enable for rx path (ensures active clock)
//############
//# WIRES
//############
//CCLK
wire cclk_reset;
wire cclk_mmcm;
wire cclk_bufio;
wire cclk_oddr;
//TX
wire tx_lclk_mmcm;
wire tx_lclk90_mmcm;
wire tx_lckl_div4_mmcm;
//MMCM & PLL
wire cclk_fb;
//wire cclk_fb_out;
wire lclk_fb_i;
wire pll_reset;
wire mmcm_locked;
reg mmcm_locked_reg;
reg mmcm_locked_sync;
wire lclk_locked;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
reg [2:0] reset_state;
reg [1:0] reset_pipe_lclkb;
reg [1:0] reset_pipe_lclk_div4b;
//wrap around counter that generates a 1 cycle heartbeat
//free running counter...
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
//two clock synchronizer
always @ (posedge sys_clk)
begin
mmcm_locked_reg <= mmcm_locked;
mmcm_locked_sync <= mmcm_locked_reg;
end
`define RESET_ALL 3'b000
`define START_CCLK 3'b001
`define STOP_CCLK 3'b010
`define DEASSERT_RESET 3'b011
`define HOLD_IT 3'b100 //???
`define ACTIVE 3'b101
//Reset sequence state machine
always @ (posedge sys_clk or posedge sys_reset)
if(sys_reset)
reset_state[2:0] <= `RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`RESET_ALL :
if(~soft_reset)
reset_state[2:0] <= `START_CCLK;
`START_CCLK :
if(mmcm_locked_sync)
reset_state[2:0] <= `STOP_CCLK;
`STOP_CCLK :
reset_state[2:0] <= `DEASSERT_RESET;
`DEASSERT_RESET :
reset_state[2:0] <= `HOLD_IT;
`HOLD_IT :
if(mmcm_locked_sync)
reset_state[2:0] <= `ACTIVE;
`ACTIVE:
if(soft_reset)
reset_state[2:0] <= `RESET_ALL; //stay there until nex reset
endcase // case (reset_state[2:0])
//reset mmcm (async)
assign mmcm_reset = (reset_state[2:0]==`RESET_ALL) |
(reset_state[2:0]==`STOP_CCLK) |
(reset_state[2:0]==`DEASSERT_RESET)
;
//reset chip (active low)
assign chip_resetb = (reset_state[2:0]==`DEASSERT_RESET) |
(reset_state[2:0]==`HOLD_IT) |
(reset_state[2:0]==`ACTIVE);
//reset the elink
wire tx_reset = (reset_state[2:0] != `ACTIVE);
assign tx_active = (reset_state[2:0] == `ACTIVE);
//#############################
//#RESET SYNC
//#############################
//async assert
//sync deassert
//lclk sync
always @ (posedge tx_lclk or posedge tx_reset)
if(tx_reset)
reset_pipe_lclkb[1:0] <= 2'b00;
else
reset_pipe_lclkb[1:0] <= {reset_pipe_lclkb[0], 1'b1};
assign etx_io_reset = ~reset_pipe_lclkb[1];
//lclkdiv4 sync
always @ (posedge tx_lclk_div4 or posedge tx_reset)
if(tx_reset)
reset_pipe_lclk_div4b[1:0] <= 2'b00;
else
reset_pipe_lclk_div4b[1:0] <= {reset_pipe_lclk_div4b[0],1'b1};
assign etx_reset = ~reset_pipe_lclk_div4b[1];
`ifdef TARGET_XILINX
//###########################
// MMCM FOR TXCLK + CCLK
//###########################
MMCME2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(MMCM_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(SYSCLK_PERIOD),
.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), //cclk_c
.CLKOUT1_DIVIDE(TXCLK_DIVIDE), //tx_lclk
.CLKOUT2_DIVIDE(TXCLK_DIVIDE), //tx_lclk90
.CLKOUT3_DIVIDE(TXCLK_DIVIDE*4), //tx_lclk_div4
.CLKOUT4_DIVIDE(128), //N/A
.CLKOUT5_DIVIDE(128), //N/A
.CLKOUT6_DIVIDE(128), //N/A
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(TXCLK_PHASE),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) mmcm_cclk
(
.CLKOUT0(cclk_mmcm),
.CLKOUT0B(),
.CLKOUT1(tx_lclk_io),
.CLKOUT1B(),
.CLKOUT2(tx_lclk90),
.CLKOUT2B(),
.CLKOUT3(tx_lclk_div4_mmcm),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.PWRDWN(1'b0),
.RST(mmcm_reset), //reset
.CLKFBIN(cclk_fb),
.CLKFBOUT(cclk_fb), //feedback clock
.CLKIN1(sys_clk), //input clock
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(mmcm_locked), //locked indicator
.PSCLK(1'b0),
.PSEN(1'b0),
.PSDONE(),
.PSINCDEC(1'b0),
.CLKFBSTOPPED(),
.CLKINSTOPPED()
);
//Tx clock buffers
BUFG i_lclk_bufg_i (.I(tx_lclk_io), .O(tx_lclk)); //300MHz
BUFG i_lclk_div4_bufg_i (.I(tx_lclk_div4_mmcm), .O(tx_lclk_div4));//75MHz
// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
//###########################
// CCLK
//###########################
//CCLK bufio
BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_mmcm));
//CCLK oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
//CCLK differential buffer
OBUFDS cclk_obuf (.O (cclk_p),
.OB (cclk_n),
.I (cclk_oddr)
);
`else // !`ifdef TARGET_XILINX
assign cclk_p = sys_clk;
assign cclk_n = sys_clk;
assign tx_lclk = sys_clk;
assign tx_lclk_div4 = sys_clk;
assign tx_lclk90 = sys_clk;
`endif // `ifdef TARGET_XILINX
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

314
parallella/fpga/parallella_base/parallella_base/src/etx_core.v
View File

@ -1,314 +0,0 @@
module etx_core(/*AUTOARG*/
// Outputs
tx_access, tx_burst, tx_packet, txrd_wait, txrr_wait, txwr_wait,
etx_cfg_access, etx_cfg_packet,
// Inputs
reset, clk, tx_io_wait, tx_rd_wait, tx_wr_wait, txrd_access,
txrd_packet, txrr_access, txrr_packet, txwr_access, txwr_packet,
etx_cfg_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
//Clocks,reset,config
input reset;
input clk;
//IO interface
output tx_access;
output tx_burst;
output [PW-1:0] tx_packet;
input tx_io_wait;
input tx_rd_wait;
input tx_wr_wait;
//TXRD
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//TXRR
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//TXWR
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
input etx_cfg_wait;
//for status?
wire[15:0] tx_status;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
wire emmu_access; // From etx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
wire etx_access; // From etx_arbiter of etx_arbiter.v
wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
wire etx_rd_wait; // From etx_protocol of etx_protocol.v
wire etx_remap_access; // From etx_remap of etx_remap.v
wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
wire etx_rr; // From etx_arbiter of etx_arbiter.v
wire etx_wr_wait; // From etx_protocol of etx_protocol.v
wire [8:0] gpio_data; // From etx_cfg of etx_cfg.v
wire gpio_enable; // From etx_cfg of etx_cfg.v
wire [14:0] mi_addr; // From etx_cfgif of ecfg_if.v
wire [DW-1:0] mi_cfg_dout; // From etx_cfg of etx_cfg.v
wire mi_cfg_en; // From etx_cfgif of ecfg_if.v
wire [63:0] mi_din; // From etx_cfgif of ecfg_if.v
wire [DW-1:0] mi_mmu_dout; // From etx_mmu of emmu.v
wire mi_mmu_en; // From etx_cfgif of ecfg_if.v
wire mi_we; // From etx_cfgif of ecfg_if.v
wire mmu_enable; // From etx_cfg of etx_cfg.v
wire remap_enable; // From etx_cfg of etx_cfg.v
wire tx_enable; // From etx_cfg of etx_cfg.v
// End of automatics
/************************************************************/
/*ELINK TRANSMIT ARBITER */
/************************************************************/
defparam etx_arbiter.ID=ID;
etx_arbiter etx_arbiter (
/*AUTOINST*/
// Outputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.txrr_wait (txrr_wait),
.etx_access (etx_access),
.etx_packet (etx_packet[PW-1:0]),
.etx_rr (etx_rr),
// Inputs
.clk (clk),
.reset (reset),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait),
.etx_cfg_wait (etx_cfg_wait),
.ctrlmode_bypass (ctrlmode_bypass),
.ctrlmode (ctrlmode[3:0]));
/************************************************************/
/* CONFIGURATOIN PACKET */
/************************************************************/
/*ecfg_if AUTO_TEMPLATE (
.\(.*\)_in (etx_\1[]),
.\(.*\)_out (etx_cfg_\1[]),
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
.wait_in (etx_cfg_wait),
);
*/
defparam etx_cfgif.RX =0;
ecfg_if etx_cfgif (.mi_dout3 (64'b0),
.mi_dout1 (64'b0),
.mi_dma_en (),
/*AUTOINST*/
// Outputs
.mi_mmu_en (mi_mmu_en),
.mi_cfg_en (mi_cfg_en),
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[63:0]),
.access_out (etx_cfg_access), // Templated
.packet_out (etx_cfg_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.access_in (etx_access), // Templated
.packet_in (etx_packet[PW-1:0]), // Templated
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
.wait_in (etx_cfg_wait)); // Templated
/************************************************************/
/* ETX CONFIGURATION REGISTERS */
/************************************************************/
/*etx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
.mi_en (mi_cfg_en),
);
*/
//todo: make more useufl
assign tx_status[15:0] = 16'b0;
/*
{2'b0, //15:14
etx_rd_wait, //13
etx_wr_wait, //12
txrr_fifo_read, //11
txrr_wait, //10
txrr_access, //9
txrd_fifo_read, //8
txrd_wait, //7
txrd_access, //6
txwr_fifo_read, //5
txwr_wait, //4
txwr_access, //3
1'b0, //2
1'b0, //1
1'b0 //0
};
*/
etx_cfg etx_cfg (
/*AUTOINST*/
// Outputs
.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
.tx_enable (tx_enable),
.mmu_enable (mmu_enable),
.gpio_enable (gpio_enable),
.remap_enable (remap_enable),
.gpio_data (gpio_data[8:0]),
.ctrlmode (ctrlmode[3:0]),
.ctrlmode_bypass (ctrlmode_bypass),
// Inputs
.reset (reset),
.clk (clk),
.mi_en (mi_cfg_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[RFAW+1:0]),
.mi_din (mi_din[31:0]),
.tx_status (tx_status[15:0]));
/************************************************************/
/* REMAPPING (SHIFT) DESTINATION ADDRESS */
/************************************************************/
/*etx_remap AUTO_TEMPLATE (
.emesh_\(.*\)_in (etx_\1[]),
.emesh_\(.*\)_out (etx_remap_\1[]),
.remap_en (remap_enable),
.remap_bypass (etx_rr),
.emesh_wait (etx_wait),
);
*/
etx_remap etx_remap (/*AUTOINST*/
// Outputs
.emesh_access_out(etx_remap_access), // Templated
.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.emesh_access_in(etx_access), // Templated
.emesh_packet_in(etx_packet[PW-1:0]), // Templated
.remap_en (remap_enable), // Templated
.remap_bypass (etx_rr), // Templated
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait));
/************************************************************/
/* EMMU */
/************************************************************/
/*emmu AUTO_TEMPLATE (
.emesh_\(.*\)_in (etx_remap_\1[]),
.emesh_\(.*\)_out (emmu_\1[]),
.mmu_en (mmu_enable),
.mmu_bp (etx_rr),
.rd_clk (clk),
.wr_clk (clk),
.emmu_access_out (emmu_access),
.emmu_packet_out (emmu_packet[PW-1:0]),
.mi_dout (mi_mmu_dout[DW-1:0]),
.emesh_wait (etx_wr_wait),
.emesh_packet_hi_out (),
.mi_en (mi_mmu_en),
);
*/
emmu etx_mmu (
/*AUTOINST*/
// Outputs
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
.emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
.emesh_packet_hi_out (), // Templated
// Inputs
.rd_clk (clk), // Templated
.wr_clk (clk), // Templated
.mmu_en (mmu_enable), // Templated
.mmu_bp (etx_rr), // Templated
.mi_en (mi_mmu_en), // Templated
.mi_we (mi_we),
.mi_addr (mi_addr[14:0]),
.mi_din (mi_din[DW-1:0]),
.emesh_access_in (etx_remap_access), // Templated
.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
.emesh_wait (etx_wr_wait)); // Templated
/************************************************************/
/*ELINK PROTOCOL LOGIC */
/************************************************************/
/*etx_protocol AUTO_TEMPLATE (
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait),
.etx_\(.*\) (emmu_\1[]),
.etx_wait (etx_wait),
);
*/
defparam etx_protocol.ID=ID;
etx_protocol etx_protocol (
/*AUTOINST*/
// Outputs
.etx_rd_wait (etx_rd_wait), // Templated
.etx_wr_wait (etx_wr_wait), // Templated
.tx_packet (tx_packet[PW-1:0]),
.tx_access (tx_access),
.tx_burst (tx_burst),
// Inputs
.reset (reset),
.clk (clk),
.etx_access (emmu_access), // Templated
.etx_packet (emmu_packet[PW-1:0]), // Templated
.tx_enable (tx_enable),
.gpio_data (gpio_data[8:0]),
.gpio_enable (gpio_enable),
.tx_io_wait (tx_io_wait),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

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module etx_fifo(/*AUTOARG*/
// Outputs
txrd_wait, txwr_wait, txrr_wait, etx_cfg_access, etx_cfg_packet,
txrd_fifo_access, txrd_fifo_packet, txrr_fifo_access,
txrr_fifo_packet, txwr_fifo_access, txwr_fifo_packet,
// Inputs
etx_reset, sys_reset, sys_clk, tx_lclk_div4, txrd_access,
txrd_packet, txwr_access, txwr_packet, txrr_access, txrr_packet,
etx_cfg_wait, txrd_fifo_wait, txrr_fifo_wait, txwr_fifo_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
//Clocks,reset,config
input etx_reset;
input sys_reset;
input sys_clk;
input tx_lclk_div4; // slow speed parallel clock
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
input etx_cfg_wait;
output txrd_fifo_access;
output [PW-1:0] txrd_fifo_packet;
input txrd_fifo_wait;
output txrr_fifo_access;
output [PW-1:0] txrr_fifo_packet;
input txrr_fifo_wait;
output txwr_fifo_access;
output [PW-1:0] txwr_fifo_packet;
input txwr_fifo_wait;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
/************************************************************/
/*FIFOs */
/************************************************************/
//TODO: Minimize depth and width
/*fifo_cdc AUTO_TEMPLATE (
// Outputs
.access_out (@"(substring vl-cell-name 0 4)"_fifo_access),
.packet_out (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
.wait_out (@"(substring vl-cell-name 0 4)"_wait),
.wait_in (@"(substring vl-cell-name 0 4)"_fifo_wait),
.clk_out (tx_lclk_div4),
.clk_in (sys_clk),
.access_in (@"(substring vl-cell-name 0 4)"_access),
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
.reset_in (sys_reset),
.reset_out (etx_reset),
.packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
);
*/
//Write fifo (from slave)
fifo_cdc #(.DW(104), .DEPTH(32)) txwr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txwr_wait), // Templated
.access_out (txwr_fifo_access), // Templated
.packet_out (txwr_fifo_packet[PW-1:0]), // Templated
// Inputs
.clk_in (sys_clk), // Templated
.reset_in (sys_reset), // Templated
.access_in (txwr_access), // Templated
.packet_in (txwr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txwr_fifo_wait)); // Templated
//Read request fifo (from slave)
fifo_cdc #(.DW(104), .DEPTH(32)) txrd_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrd_wait), // Templated
.access_out (txrd_fifo_access), // Templated
.packet_out (txrd_fifo_packet[PW-1:0]), // Templated
// Inputs
.clk_in (sys_clk), // Templated
.reset_in (sys_reset), // Templated
.access_in (txrd_access), // Templated
.packet_in (txrd_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txrd_fifo_wait)); // Templated
//Read response fifo (from master)
fifo_cdc #(.DW(104), .DEPTH(32)) txrr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrr_wait), // Templated
.access_out (txrr_fifo_access), // Templated
.packet_out (txrr_fifo_packet[PW-1:0]), // Templated
// Inputs
.clk_in (sys_clk), // Templated
.reset_in (sys_reset), // Templated
.access_in (txrr_access), // Templated
.packet_in (txrr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txrr_fifo_wait)); // Templated
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

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module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
// Inputs
reset, tx_lclk, tx_lclk_io, tx_lclk90, txi_wr_wait_p,
txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access,
tx_burst
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
//###########
//# reset, clocks
//##########
input reset; //sync reset for io
input tx_lclk; //fast clock for io state machine
input tx_lclk_io; //fast ODDR
input tx_lclk90; //fast 90deg shifted lclk
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
//#############
//# Fabric interface
//#############
input [PW-1:0] tx_packet;
input tx_access;
input tx_burst;
output tx_io_wait;
output tx_wr_wait;
output tx_rd_wait;
//############
//# REGS
//############
reg [7:0] tx_pointer;
reg [15:0] tx_data16;
reg tx_access_reg;
reg tx_frame;
reg tx_io_wait_reg;
reg [PW-1:0] tx_packet_reg;
reg [63:0] tx_double;
reg [2:0] tx_state_reg;
reg [2:0] tx_state;
//############
//# WIRES
//############
wire new_tran;
wire access;
wire write;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [7:0] txo_data;
wire txo_frame;
wire txo_lclk90;
reg tx_io_wait;
//#############################
//# Transmit state machine
//#############################
`define IDLE 3'b000
`define CYCLE1 3'b001
`define CYCLE2 3'b010
`define CYCLE3 3'b011
`define CYCLE4 3'b100
`define CYCLE5 3'b101
`define CYCLE6 3'b110
`define CYCLE7 3'b111
always @ (posedge tx_lclk)
if(reset)
tx_state[2:0] <= `IDLE;
else
case (tx_state[2:0])
`IDLE : tx_state[2:0] <= tx_access ? `CYCLE1 : `IDLE;
`CYCLE1 : tx_state[2:0] <= `CYCLE2;
`CYCLE2 : tx_state[2:0] <= `CYCLE3;
`CYCLE3 : tx_state[2:0] <= `CYCLE4;
`CYCLE4 : tx_state[2:0] <= `CYCLE5;
`CYCLE5 : tx_state[2:0] <= `CYCLE6;
`CYCLE6 : tx_state[2:0] <= `CYCLE7;
`CYCLE7 : tx_state[2:0] <= tx_burst ? `CYCLE4 : `IDLE;
endcase // case (tx_state)
assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
//Creating wait pulse for slow clock domain
always @ (posedge tx_lclk)
if(reset | ~tx_access)
tx_io_wait <= 1'b0;
else if ((tx_state[2:0] ==`CYCLE4) & ~tx_burst)
tx_io_wait <= 1'b1;
else if (tx_state[2:0]==`IDLE)
tx_io_wait <= 1'b0;
//Create frame signal for output
always @ (posedge tx_lclk)
begin
tx_state_reg[2:0] <= tx_state[2:0];
tx_frame <= |(tx_state_reg[2:0]);
end
//#############################
//# 2 CYCLE PACKET PIPELINE
//#############################
always @ (posedge tx_lclk)
if (tx_access)
tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
packet2emesh p2e (
.write_out (write),
.datamode_out (datamode[1:0]),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (tx_packet_reg[PW-1:0]));
/*
* The following format is used by the Epiphany multicore ASIC.
* Don't change it if you want to communicate with Epiphany.
*
*/
always @ (posedge tx_lclk)
if (tx_new_frame)
tx_double[63:0] <= {16'b0,//16
~write,7'b0,ctrlmode[3:0],//12
dstaddr[31:0],datamode[1:0],write,tx_access};//36
else if(tx_state[2:0]==`CYCLE4)
tx_double[63:0] <= {data[31:0],srcaddr[31:0]};
//#############################
//# SELECTING DATA FOR TRANSMIT
//#############################
always @ (posedge tx_lclk)
case(tx_state_reg[2:0])
//Cycle1
3'b001: tx_data16[15:0] <= tx_double[47:32];
//Cycle2
3'b010: tx_data16[15:0] <= tx_double[31:16];
//Cycle3
3'b011: tx_data16[15:0] <= tx_double[15:0];
//Cycle4
3'b100: tx_data16[15:0] <= tx_double[63:48];
//Cycle5
3'b101: tx_data16[15:0] <= tx_double[47:32];
//Cycle6
3'b110: tx_data16[15:0] <= tx_double[31:16];
//Cycle7
3'b111: tx_data16[15:0] <= tx_double[15:0];
default tx_data16[15:0] <= 16'b0;
endcase // case (tx_state[2:0])
//#############################
//# CLOCK DRIVERS
//#############################
BUFIO i_lclk (.I(tx_lclk_io), .O(tx_lclk_ddr));
BUFIO i_lclk90 (.I(tx_lclk90), .O(tx_lclk90_ddr));
//#############################
//# ODDR DRIVERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data[i]),
.C (tx_lclk_ddr),
.CE (1'b1),
.D1 (tx_data16[i+8]),
.D2 (tx_data16[i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_frame (
.Q (txo_frame),
.C (tx_lclk_ddr),
.CE (1'b1),
.D1 (tx_frame),
.D2 (tx_frame),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90_ddr),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
//##############################
//# OUTPUT BUFFERS
//##############################
OBUFDS obufds_data[7:0] (
.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data[7:0])
);
OBUFDS obufds_frame ( .O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame)
);
OBUFDS obufds_lclk ( .O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90)
);
//################################
//# Wait Input Buffers
//################################
generate
if(ETYPE==1)
begin
assign tx_wr_wait = txi_wr_wait_p;
end
else if (ETYPE==0)
begin
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_wrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait));
end
endgenerate
//TODO: Come up with cleaner defines for this
//Parallella and other platforms...
`ifdef TODO
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rdwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait));
`else
//On Parallella this signal comes in single-ended
assign tx_rd_wait = txi_rd_wait_p;
`endif
endmodule // etx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

181
parallella/fpga/parallella_base/parallella_base/src/etx_protocol.v
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`include "elink_regmap.v"
module etx_protocol (/*AUTOARG*/
// Outputs
etx_rd_wait, etx_wr_wait, tx_packet, tx_access, tx_burst,
// Inputs
reset, clk, etx_access, etx_packet, tx_enable, gpio_data,
gpio_enable, tx_io_wait, tx_rd_wait, tx_wr_wait
);
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h000;
//Clock/reset
input reset;
input clk;
//System side
input etx_access;
input [PW-1:0] etx_packet;
//Pushback signals
output etx_rd_wait;
output etx_wr_wait;
//Enble transmit
input tx_enable; //transmit enable
input [8:0] gpio_data; //TODO
input gpio_enable; //TODO
//Interface to IO
output [PW-1:0] tx_packet;
output tx_access;
output tx_burst;
input tx_io_wait;
input tx_rd_wait; // The wait signals are passed through
input tx_wr_wait; // to the emesh interfaces
//###################################################################
//# Local regs & wires
//###################################################################
reg tx_burst;
reg tx_access;
reg [PW-1:0] tx_packet;
wire tx_rd_wait_sync;
wire tx_wr_wait_sync;
wire etx_write;
wire [1:0] etx_datamode;
wire [3:0] etx_ctrlmode;
wire [AW-1:0] etx_dstaddr;
wire [DW-1:0] etx_data;
wire last_write;
wire [1:0] last_datamode;
wire [3:0] last_ctrlmode;
wire [AW-1:0] last_dstaddr;
wire etx_valid;
reg etx_io_wait;
wire burst_match;
wire burst_type_match;
wire [31:0] burst_addr;
wire burst_addr_match;
//packet to emesh bundle
packet2emesh p2m0 (
.write_out (etx_write),
.datamode_out (etx_datamode[1:0]),
.ctrlmode_out (etx_ctrlmode[3:0]),
.dstaddr_out (etx_dstaddr[31:0]),
.data_out (),
.srcaddr_out (),
.packet_in (etx_packet[PW-1:0]));//input
//Only set valid if not wait and
assign etx_valid = (tx_enable &
etx_access &
~((etx_dstaddr[31:20]==ID) & (etx_dstaddr[19:16]!=`EGROUP_RR)) &
((etx_write & ~tx_wr_wait_sync) | (~etx_write & ~tx_rd_wait_sync))
);
reg tx_io_wait_reg;
//Pipeline the io wait to improve timing
always @ (posedge clk)
tx_io_wait_reg <= tx_io_wait;
//Prepare transaction / with burst
always @ (posedge clk)
if(reset)
begin
tx_packet[PW-1:0] <= 'b0;
tx_access <= 1'b0;
end
else if(~tx_io_wait)
begin
tx_packet[PW-1:0] <= etx_packet[PW-1:0];
tx_access <= etx_valid;
end
always @ (posedge clk)
if(reset)
tx_burst <= 1'b0;
else
tx_burst <= (etx_write & //write
(etx_datamode[1:0]==2'b11) & //double only
burst_type_match & //same types
burst_addr_match); //inc by 8
//#############################
//# Burst Detection
//#############################
packet2emesh p2m1 (
.write_out (last_write),
.datamode_out (last_datamode[1:0]),
.ctrlmode_out (last_ctrlmode[3:0]),
.dstaddr_out (last_dstaddr[31:0]),
.data_out (),
.srcaddr_out (),
.packet_in (tx_packet[PW-1:0]));//input
assign burst_addr[31:0] = (last_dstaddr[31:0] + 4'd8);
assign burst_addr_match = (burst_addr[31:0] == etx_dstaddr[31:0]);
assign burst_type_match = {last_ctrlmode[3:0],last_datamode[1:0],last_write}
==
{etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
//#############################
//# Wait signals (async)
//#############################
synchronizer #(.DW(1)) rd_sync (// Outputs
.out (tx_rd_wait_sync),
// Inputs
.in (tx_rd_wait),
.clk (clk),
.reset (reset)
);
synchronizer #(.DW(1)) wr_sync (// Outputs
.out (tx_wr_wait_sync),
// Inputs
.in (tx_wr_wait),
.clk (clk),
.reset (reset)
);
//Stall for all etx pipeline
assign etx_wr_wait = tx_wr_wait_sync | tx_io_wait;
assign etx_rd_wait = tx_rd_wait_sync | tx_io_wait;
endmodule // etx_protocol
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

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module etx_remap (/*AUTOARG*/
// Outputs
emesh_access_out, emesh_packet_out,
// Inputs
clk, reset, emesh_access_in, emesh_packet_in, remap_en,
remap_bypass, etx_rd_wait, etx_wr_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h808;
//Clock/reset
input clk;
input reset;
//Input from arbiter
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
input remap_en; //enable tx remap (static)
input remap_bypass; //dynamic control (read request)
//Output to TX IO
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
//Wait signals from protocol block
input etx_rd_wait;
input etx_wr_wait;
wire [31:0] addr_in;
wire [31:0] addr_remap;
wire [31:0] addr_out;
wire write_in;
reg emesh_access_out;
reg [PW-1:0] emesh_packet_out;
assign addr_in[31:0] = emesh_packet_in[39:8];
assign write_in = emesh_packet_in[1];
assign addr_remap[31:0] = {addr_in[29:18],//ID
addr_in[17:16],//SPECIAL GROUP
{(2){(|addr_in[17:16])}},//ZERO IF NOT SPECIAL
addr_in[15:0]
};
assign addr_out[31:0] = (remap_en & ~remap_bypass) ? addr_remap[31:0] :
addr_in[31:0];
//stall read/write access appropriately
always @ (posedge clk)
if((write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
begin
emesh_access_out <= emesh_access_in;
emesh_packet_out[PW-1:0] <= {emesh_packet_in[PW-1:40],
addr_out[31:0],
emesh_packet_in[7:0]
};
end
endmodule // etx_mux

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module fifo_async
(/*AUTOARG*/
// Outputs
full, prog_full, dout, empty, valid,
// Inputs
wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104; //FIFO width
parameter DEPTH = 32; //FIFO depth
parameter TYPE = "XILINX";//"BASIC" or "XILINX" or "ALTERA"
//##########
//# RESET/CLOCK
//##########
input wr_rst; //write reset
input rd_rst; //read reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
generate
if(TYPE=="BASIC") begin : basic
fifo_async_model
#(.DEPTH(DEPTH),
.DW(DW))
fifo_model (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
else if (TYPE=="XILINX") begin : xilinx
if((DW==104) & (DEPTH==32))
begin
fifo_async_104x32 fifo_async_104x32 (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end // if ((DW==104) & (DEPTH==32))
end // block: xilinx
endgenerate
endmodule // fifo_async
// Local Variables:
// verilog-library-directories:("." "../ip/xilinx/" "../dv")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

403
parallella/fpga/parallella_base/parallella_base/src/fifo_async_104x32/fifo_async_104x32.xci
View File

@ -1,403 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
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90
parallella/fpga/parallella_base/parallella_base/src/fifo_cdc.v
View File

@ -1,90 +0,0 @@
/*
########################################################################
Generic Clock Domain Crossing Block
########################################################################
*/
module fifo_cdc (/*AUTOARG*/
// Outputs
wait_out, access_out, packet_out,
// Inputs
clk_in, reset_in, access_in, packet_in, clk_out, reset_out,
wait_in
);
parameter DW = 104;
parameter DEPTH = 32;
/********************************/
/*Incoming Packet */
/********************************/
input clk_in;
input reset_in;
input access_in;
input [DW-1:0] packet_in;
output wait_out;
/********************************/
/*Outgoing Packet */
/********************************/
input clk_out;
input reset_out;
output access_out;
output [DW-1:0] packet_out;
input wait_in;
//Local wires
wire wr_en;
wire rd_en;
wire empty;
wire full;
wire valid;
reg access_out;
assign wr_en = access_in & ~full;
assign rd_en = ~empty & ~wait_in;
assign wait_out = full;
//Keep access high until "acknowledge"
always @ (posedge clk_out or posedge reset_out)
if(reset_out)
access_out <=1'b0;
else if(~wait_in)
access_out <=rd_en;
//Read response fifo (from master)
defparam fifo.DW = DW;
defparam fifo.DEPTH = DEPTH;
fifo_async fifo (.prog_full (full),//stay safe for now
.full (),
// Outputs
.dout (packet_out[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (reset_in),
.rd_rst (reset_out),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en)
);
endmodule // fifo_cdc
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

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/*
########################################################################
Generic small FIFO using distributed memory
Caution: There is no protection against overflow or underflow,
driving logic should avoid wen on full or ren on empty.
########################################################################
*/
module fifo_sync
#(
// Address width (must be 5 => 32-deep FIFO)
parameter AW = 5,
// Data width
parameter DW = 16
)
(
input clk,
input reset,
input [DW-1:0] wr_data,
input wr_en,
input rd_en,
output wire [DW-1:0] rd_data,
output reg rd_empty,
output reg wr_full
);
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
reg [AW-1:0] count;
always @ ( posedge clk or posedge reset ) begin
if( reset )
begin
wr_addr[AW-1:0] <= 'd0;
rd_addr[AW-1:0] <= 'b0;
count[AW-1:0] <= 'b0;
rd_empty <= 1'b1;
wr_full <= 1'b0;
end else
begin
if( wr_en & rd_en )
begin
wr_addr <= wr_addr + 'd1;
rd_addr <= rd_addr + 'd1;
end
else if( wr_en )
begin
wr_addr <= wr_addr + 'd1;
count <= count + 'd1;
rd_empty <= 1'b0;
if( & count )
wr_full <= 1'b1;
end
else if( rd_en )
begin
rd_addr <= rd_addr + 'd1;
count <= count - 'd1;
wr_full <= 1'b0;
if( count == 'd1 )
rd_empty <= 1'b1;
end
end // else: !if( reset )
end // always @ ( posedge clk )
defparam mem.DW=DW;
defparam mem.AW=AW;
memory_dp mem (
// Outputs
.rd_data (rd_data[DW-1:0]),
// Inputs
.wr_clk (clk),
.wr_en ({(DW/8){wr_en}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_data (wr_data[DW-1:0]),
.rd_clk (clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]));
endmodule // fifo_sync
// Local Variables:
// verilog-library-directories:(".")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

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/*###########################################################################
# Function: Dual port memory wrapper (one read/ one write port)
# To run without hardware platform dependancy, `define:
# "TARGET_CLEAN"
############################################################################
*/
module memory_dp(/*AUTOARG*/
// Outputs
rd_data,
// Inputs
wr_clk, wr_en, wr_addr, wr_data, rd_clk, rd_en, rd_addr
);
parameter AW = 14;
parameter DW = 32;
parameter WED = DW/8; //one per byte
parameter MD = 1<<AW;//memory depth
//write-port
input wr_clk; //write clock
input [WED-1:0] wr_en; //write enable vector
input [AW-1:0] wr_addr;//write address
input [DW-1:0] wr_data;//write data
//read-port
input rd_clk; //read clock
input rd_en; //read enable
input [AW-1:0] rd_addr;//read address
output[DW-1:0] rd_data;//read output data
//////////////////////
//SIMPLE MEMORY MODEL
//////////////////////
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
//read port
always @ (posedge rd_clk)
if(rd_en)
rd_data[DW-1:0] <= ram[rd_addr[AW-1:0]];
//write port
generate
genvar i;
for (i = 0; i < WED; i = i+1) begin: gen_ram
always @(posedge wr_clk)
begin
if (wr_en[i])
ram[wr_addr[AW-1:0]][(i+1)*8-1:i*8] <= wr_data[(i+1)*8-1:i*8];
end
end
endgenerate
endmodule // memory_dp
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

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module packet2emesh(/*AUTOARG*/
// Outputs
write_out, datamode_out, ctrlmode_out, data_out, dstaddr_out,
srcaddr_out,
// Inputs
packet_in
);
parameter PW = 104; //packet width
parameter DW = 32; //data width
parameter AW = 32; //addess width
//Input packet
input [PW-1:0] packet_in;
//Emesh signal bundle
output write_out;
output [1:0] datamode_out;
output [3:0] ctrlmode_out;
output [DW-1:0] data_out; //TODO: fix to make relative to PW
output [AW-1:0] dstaddr_out;
output [AW-1:0] srcaddr_out;
assign write_out = packet_in[0];
assign datamode_out[1:0] = packet_in[2:1];
assign ctrlmode_out[3:0] = packet_in[6:3];
assign dstaddr_out[31:0] = packet_in[39:8];
assign srcaddr_out[31:0] = packet_in[103:72];
assign data_out[31:0] = packet_in[71:40];
endmodule // packet2emesh
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

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//NOTE: module name differs from file name to simplify Vivado block design
//Many verilog versions to one block design...
module parallella(/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, timeout, s_axi_wready, s_axi_rvalid, s_axi_rresp,
s_axi_rlast, s_axi_rid, s_axi_rdata, s_axi_bvalid, s_axi_bresp,
s_axi_bid, s_axi_awready, s_axi_arready, rxo_wr_wait_p,
rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, ps_gpio_i,
m_axi_wvalid, m_axi_wstrb, m_axi_wlast, m_axi_wid, m_axi_wdata,
m_axi_rready, m_axi_bready, m_axi_awvalid, m_axi_awsize,
m_axi_awqos, m_axi_awprot, m_axi_awlock, m_axi_awlen, m_axi_awid,
m_axi_awcache, m_axi_awburst, m_axi_awaddr, m_axi_arvalid,
m_axi_arsize, m_axi_arqos, m_axi_arprot, m_axi_arlock, m_axi_arlen,
m_axi_arid, m_axi_arcache, m_axi_arburst, m_axi_araddr, i2c_sda_i,
i2c_scl_i, elink_active, chipid, chip_resetb, cclk_p, cclk_n,
mailbox_not_empty,
// Inouts
i2c_sda, i2c_scl, gpio_p, gpio_n,
// Inputs
txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
sys_clk, s_axi_wvalid, s_axi_wstrb, s_axi_wlast, s_axi_wid,
s_axi_wdata, s_axi_rready, s_axi_bready, s_axi_awvalid,
s_axi_awsize, s_axi_awqos, s_axi_awprot, s_axi_awlock, s_axi_awlen,
s_axi_awid, s_axi_awcache, s_axi_awburst, s_axi_awaddr,
s_axi_arvalid, s_axi_arsize, s_axi_arqos, s_axi_arprot,
s_axi_arlock, s_axi_arlen, s_axi_arid, s_axi_aresetn,
s_axi_arcache, s_axi_arburst, s_axi_araddr, rxi_lclk_p, rxi_lclk_n,
rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, reset, ps_gpio_t,
ps_gpio_o, m_axi_wready, m_axi_rvalid, m_axi_rresp, m_axi_rlast,
m_axi_rid, m_axi_rdata, m_axi_bvalid, m_axi_bresp, m_axi_bid,
m_axi_awready, m_axi_arready, m_axi_aresetn, i2c_sda_t, i2c_sda_o,
i2c_scl_t, i2c_scl_o
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 0;
parameter NGPIO = 24;
parameter NPS = 64; //Number of PS signals
output mailbox_not_empty; // From axe_elink of axi_elink.v
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout [NGPIO-1:0] gpio_n; // To/From pgpio of pgpio.v
inout [NGPIO-1:0] gpio_p; // To/From pgpio of pgpio.v
inout i2c_scl; // To/From pi2c of pi2c.v
inout i2c_sda; // To/From pi2c of pi2c.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cclk_n; // From axe_elink of axi_elink.v
output cclk_p; // From axe_elink of axi_elink.v
output chip_resetb; // From axe_elink of axi_elink.v
output [11:0] chipid; // From axe_elink of axi_elink.v
output elink_active; // From axe_elink of axi_elink.v
output i2c_scl_i; // From pi2c of pi2c.v
output i2c_sda_i; // From pi2c of pi2c.v
output [31:0] m_axi_araddr; // From axe_elink of axi_elink.v
output [1:0] m_axi_arburst; // From axe_elink of axi_elink.v
output [3:0] m_axi_arcache; // From axe_elink of axi_elink.v
output [M_IDW-1:0] m_axi_arid; // From axe_elink of axi_elink.v
output [7:0] m_axi_arlen; // From axe_elink of axi_elink.v
output [1:0] m_axi_arlock; // From axe_elink of axi_elink.v
output [2:0] m_axi_arprot; // From axe_elink of axi_elink.v
output [3:0] m_axi_arqos; // From axe_elink of axi_elink.v
output [2:0] m_axi_arsize; // From axe_elink of axi_elink.v
output m_axi_arvalid; // From axe_elink of axi_elink.v
output [31:0] m_axi_awaddr; // From axe_elink of axi_elink.v
output [1:0] m_axi_awburst; // From axe_elink of axi_elink.v
output [3:0] m_axi_awcache; // From axe_elink of axi_elink.v
output [M_IDW-1:0] m_axi_awid; // From axe_elink of axi_elink.v
output [7:0] m_axi_awlen; // From axe_elink of axi_elink.v
output [1:0] m_axi_awlock; // From axe_elink of axi_elink.v
output [2:0] m_axi_awprot; // From axe_elink of axi_elink.v
output [3:0] m_axi_awqos; // From axe_elink of axi_elink.v
output [2:0] m_axi_awsize; // From axe_elink of axi_elink.v
output m_axi_awvalid; // From axe_elink of axi_elink.v
output m_axi_bready; // From axe_elink of axi_elink.v
output m_axi_rready; // From axe_elink of axi_elink.v
output [63:0] m_axi_wdata; // From axe_elink of axi_elink.v
output [M_IDW-1:0] m_axi_wid; // From axe_elink of axi_elink.v
output m_axi_wlast; // From axe_elink of axi_elink.v
output [7:0] m_axi_wstrb; // From axe_elink of axi_elink.v
output m_axi_wvalid; // From axe_elink of axi_elink.v
output [NPS-1:0] ps_gpio_i; // From pgpio of pgpio.v
output rxo_rd_wait_n; // From axe_elink of axi_elink.v
output rxo_rd_wait_p; // From axe_elink of axi_elink.v
output rxo_wr_wait_n; // From axe_elink of axi_elink.v
output rxo_wr_wait_p; // From axe_elink of axi_elink.v
output s_axi_arready; // From axe_elink of axi_elink.v
output s_axi_awready; // From axe_elink of axi_elink.v
output [S_IDW-1:0] s_axi_bid; // From axe_elink of axi_elink.v
output [1:0] s_axi_bresp; // From axe_elink of axi_elink.v
output s_axi_bvalid; // From axe_elink of axi_elink.v
output [31:0] s_axi_rdata; // From axe_elink of axi_elink.v
output [S_IDW-1:0] s_axi_rid; // From axe_elink of axi_elink.v
output s_axi_rlast; // From axe_elink of axi_elink.v
output [1:0] s_axi_rresp; // From axe_elink of axi_elink.v
output s_axi_rvalid; // From axe_elink of axi_elink.v
output s_axi_wready; // From axe_elink of axi_elink.v
output timeout; // From axe_elink of axi_elink.v
output [7:0] txo_data_n; // From axe_elink of axi_elink.v
output [7:0] txo_data_p; // From axe_elink of axi_elink.v
output txo_frame_n; // From axe_elink of axi_elink.v
output txo_frame_p; // From axe_elink of axi_elink.v
output txo_lclk_n; // From axe_elink of axi_elink.v
output txo_lclk_p; // From axe_elink of axi_elink.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input i2c_scl_o; // To pi2c of pi2c.v
input i2c_scl_t; // To pi2c of pi2c.v
input i2c_sda_o; // To pi2c of pi2c.v
input i2c_sda_t; // To pi2c of pi2c.v
input m_axi_aresetn; // To axe_elink of axi_elink.v
input m_axi_arready; // To axe_elink of axi_elink.v
input m_axi_awready; // To axe_elink of axi_elink.v
input [M_IDW-1:0] m_axi_bid; // To axe_elink of axi_elink.v
input [1:0] m_axi_bresp; // To axe_elink of axi_elink.v
input m_axi_bvalid; // To axe_elink of axi_elink.v
input [63:0] m_axi_rdata; // To axe_elink of axi_elink.v
input [M_IDW-1:0] m_axi_rid; // To axe_elink of axi_elink.v
input m_axi_rlast; // To axe_elink of axi_elink.v
input [1:0] m_axi_rresp; // To axe_elink of axi_elink.v
input m_axi_rvalid; // To axe_elink of axi_elink.v
input m_axi_wready; // To axe_elink of axi_elink.v
input [NPS-1:0] ps_gpio_o; // To pgpio of pgpio.v
input [NPS-1:0] ps_gpio_t; // To pgpio of pgpio.v
input reset; // To axe_elink of axi_elink.v
input [7:0] rxi_data_n; // To axe_elink of axi_elink.v
input [7:0] rxi_data_p; // To axe_elink of axi_elink.v
input rxi_frame_n; // To axe_elink of axi_elink.v
input rxi_frame_p; // To axe_elink of axi_elink.v
input rxi_lclk_n; // To axe_elink of axi_elink.v
input rxi_lclk_p; // To axe_elink of axi_elink.v
input [31:0] s_axi_araddr; // To axe_elink of axi_elink.v
input [1:0] s_axi_arburst; // To axe_elink of axi_elink.v
input [3:0] s_axi_arcache; // To axe_elink of axi_elink.v
input s_axi_aresetn; // To axe_elink of axi_elink.v
input [S_IDW-1:0] s_axi_arid; // To axe_elink of axi_elink.v
input [7:0] s_axi_arlen; // To axe_elink of axi_elink.v
input [1:0] s_axi_arlock; // To axe_elink of axi_elink.v
input [2:0] s_axi_arprot; // To axe_elink of axi_elink.v
input [3:0] s_axi_arqos; // To axe_elink of axi_elink.v
input [2:0] s_axi_arsize; // To axe_elink of axi_elink.v
input s_axi_arvalid; // To axe_elink of axi_elink.v
input [31:0] s_axi_awaddr; // To axe_elink of axi_elink.v
input [1:0] s_axi_awburst; // To axe_elink of axi_elink.v
input [3:0] s_axi_awcache; // To axe_elink of axi_elink.v
input [S_IDW-1:0] s_axi_awid; // To axe_elink of axi_elink.v
input [7:0] s_axi_awlen; // To axe_elink of axi_elink.v
input [1:0] s_axi_awlock; // To axe_elink of axi_elink.v
input [2:0] s_axi_awprot; // To axe_elink of axi_elink.v
input [3:0] s_axi_awqos; // To axe_elink of axi_elink.v
input [2:0] s_axi_awsize; // To axe_elink of axi_elink.v
input s_axi_awvalid; // To axe_elink of axi_elink.v
input s_axi_bready; // To axe_elink of axi_elink.v
input s_axi_rready; // To axe_elink of axi_elink.v
input [31:0] s_axi_wdata; // To axe_elink of axi_elink.v
input [S_IDW-1:0] s_axi_wid; // To axe_elink of axi_elink.v
input s_axi_wlast; // To axe_elink of axi_elink.v
input [3:0] s_axi_wstrb; // To axe_elink of axi_elink.v
input s_axi_wvalid; // To axe_elink of axi_elink.v
input sys_clk; // To axe_elink of axi_elink.v
input txi_rd_wait_n; // To axe_elink of axi_elink.v
input txi_rd_wait_p; // To axe_elink of axi_elink.v
input txi_wr_wait_n; // To axe_elink of axi_elink.v
input txi_wr_wait_p; // To axe_elink of axi_elink.v
// End of automatics
/*AUTOWIRE*/
axi_elink axe_elink (.mailbox_full (),
/*AUTOINST*/
// Outputs
.elink_active (elink_active),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.chipid (chipid[11:0]),
.chip_resetb (chip_resetb),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.mailbox_not_empty(mailbox_not_empty),
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock[1:0]),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock[1:0]),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
.timeout (timeout),
// Inputs
.reset (reset),
.sys_clk (sys_clk),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.m_axi_aresetn (m_axi_aresetn),
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
.m_axi_rdata (m_axi_rdata[63:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock[1:0]),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock[1:0]),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
pgpio pgpio (/*AUTOINST*/
// Outputs
.ps_gpio_i (ps_gpio_i[NPS-1:0]),
// Inouts
.gpio_p (gpio_p[NGPIO-1:0]),
.gpio_n (gpio_n[NGPIO-1:0]),
// Inputs
.ps_gpio_o (ps_gpio_o[NPS-1:0]),
.ps_gpio_t (ps_gpio_t[NPS-1:0]));
pi2c pi2c (/*AUTOINST*/
// Outputs
.i2c_sda_i (i2c_sda_i),
.i2c_scl_i (i2c_scl_i),
// Inouts
.i2c_sda (i2c_sda),
.i2c_scl (i2c_scl),
// Inputs
.i2c_sda_o (i2c_sda_o),
.i2c_sda_t (i2c_sda_t),
.i2c_scl_o (i2c_scl_o),
.i2c_scl_t (i2c_scl_t));
endmodule // parallella_generic
// Local Variables:
// verilog-library-directories:("." "../../elink/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/

136
parallella/fpga/parallella_base/parallella_base/src/pgpio.v
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@ -1,136 +0,0 @@
// Implements GPIO pins from the PS/EMIO
// Works with 7010 (24 pins) or 7020 (48 pins) and
// either single-ended or differential IO
module pgpio(/*AUTOARG*/
// Outputs
ps_gpio_i,
// Inouts
gpio_p, gpio_n,
// Inputs
ps_gpio_o, ps_gpio_t
);
parameter NGPIO = 24; // 12 or 24
parameter NPS = 64; // signals for PS
parameter DIFF = 0; // 0= single ended
// 1= differential
inout [NGPIO-1:0] gpio_p;
inout [NGPIO-1:0] gpio_n;
output [NPS-1:0] ps_gpio_i;
input [NPS-1:0] ps_gpio_o;
input [NPS-1:0] ps_gpio_t;
genvar m;
generate
if( DIFF == 1 ) begin: gpio_diff
IOBUFDS
#(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("LVDS_25"),
.SLEW("FAST")
)
i_iodiff [NGPIO-1:0]
(
.O(ps_gpio_i), // Buffer output
.IO(gpio_p), // Diff_p inout (connect directly to top-level port)
.IOB(gpio_n), // Diff_n inout (connect directly to top-level port)
.I(ps_gpio_o), // Buffer input
.T(ps_gpio_t) // 3-state enable input, high=input, low=output
);
end else begin: gpio_cmos // single-ended
wire [NGPIO-1:0] gpio_i_n, gpio_i_p;
wire [NGPIO-1:0] gpio_o_n, gpio_o_p;
wire [NGPIO-1:0] gpio_t_n, gpio_t_p;
// Map P/N pins to single-ended signals
for(m=0; m<NGPIO; m=m+2) begin : assign_se_sigs
assign ps_gpio_i[2*m] = gpio_i_n[m];
assign ps_gpio_i[2*m+1] = gpio_i_n[m+1];
assign ps_gpio_i[2*m+2] = gpio_i_p[m];
assign ps_gpio_i[2*m+3] = gpio_i_p[m+1];
assign gpio_o_n[m] = ps_gpio_o[2*m];
assign gpio_o_n[m+1] = ps_gpio_o[2*m+1];
assign gpio_o_p[m] = ps_gpio_o[2*m+2];
assign gpio_o_p[m+1] = ps_gpio_o[2*m+3];
assign gpio_t_n[m] = ps_gpio_t[2*m];
assign gpio_t_n[m+1] = ps_gpio_t[2*m+1];
assign gpio_t_p[m] = ps_gpio_t[2*m+2];
assign gpio_t_p[m+1] = ps_gpio_t[2*m+3];
end // block: assign_se_sigs
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
i_iocmos_n [NGPIO-1:0]
(
.O(gpio_i_n), // Buffer output
.IO(gpio_n), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_n), // Buffer input
.T(gpio_t_n) // 3-state enable input, high=input, low=output
);
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
i_iocmos_p [NGPIO-1:0]
(
.O(gpio_i_p), // Buffer output
.IO(gpio_p), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_p), // Buffer input
.T(gpio_t_p) // 3-state enable input, high=input, low=output
);
end // block: GPIO_SE
endgenerate
// Tie off unused PS EMIO signals for now
genvar i;
generate
for (i=NGPIO*2;i<NPS;i=i+1)
assign ps_gpio_i = 1'b0;
endgenerate
endmodule // parallella_gpio_emio
/*
File: parallella_gpio_emio.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2014 Adapteva, Inc.
Contributed by Fred Huettig
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

85
parallella/fpga/parallella_base/parallella_base/src/pi2c.v
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@ -1,85 +0,0 @@
module pi2c (/*AUTOARG*/
// Outputs
i2c_sda_i, i2c_scl_i,
// Inouts
i2c_sda, i2c_scl,
// Inputs
i2c_sda_o, i2c_sda_t, i2c_scl_o, i2c_scl_t
);
parameter PORTABLE = 0;
input i2c_sda_o;
input i2c_sda_t;
output i2c_sda_i;
input i2c_scl_o;
input i2c_scl_t;
output i2c_scl_i;
inout i2c_sda;
inout i2c_scl;
generate
if(PORTABLE==1) begin
wire i2c_sda = i2c_sda_t ? 1'bz: i2c_sda_o;
wire i2c_sda_i = i2c_sda;
wire i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
wire i2c_scl_i = i2c_scl;
end
else
begin
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) i_sda (
.O(i2c_sda_i), // Buffer output
.IO(i2c_sda), // Buffer inout port (connect directly to top-level port)
.I(i2c_sda_o), // Buffer input
.T(i2c_sda_t) // 3-state enable input, high=input, low=output
);
IOBUF #(
.DRIVE(8),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) i_scl (
.O(i2c_scl_i),
.IO(i2c_scl),
.I(i2c_scl_o),
.T(i2c_scl_t)
);
end
endgenerate
endmodule // pi2c
/*
File: parallella_i2c
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2015 Adapteva, Inc.
Contributed by Fred Huettig
Contributed by Andreas Olofsson
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

30
parallella/fpga/parallella_base/parallella_base/src/pulse_stretcher.v
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@ -1,30 +0,0 @@
/*
* This module stretches a pulse by DW+1 clock cycles
* Can be useful for synchronous clock transfers from fast to slow.
*
*/
module pulse_stretcher (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, in
);
parameter DW = 1;
input clk;
input reset;
input in;
output out;
reg [DW-1:0] wide_pulse;
always @ (posedge clk)
wide_pulse[DW-1:0] <= {wide_pulse[DW-2:0],in};
assign out = (|{wide_pulse[DW-1:0],in});
endmodule // pulse_stretcher

60
parallella/fpga/parallella_base/parallella_base/src/synchronizer.v
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@ -1,60 +0,0 @@
/*
#######################################################
# Synchronizer circuit
#######################################################
*/
module synchronizer (/*AUTOARG*/
// Outputs
out,
// Inputs
in, clk, reset
);
parameter DW = 1;
//Input Side
input [DW-1:0] in;
input clk;
input reset;
//Output Side
output [DW-1:0] out;
//Three stages
reg [DW-1:0] sync_reg0;
reg [DW-1:0] out;
//We use two flip-flops for metastability improvement
always @ (posedge clk or posedge reset)
if(reset)
begin
sync_reg0[DW-1:0] <= {(DW){1'b0}};
out[DW-1:0] <= {(DW){1'b0}};
end
else
begin
sync_reg0[DW-1:0] <= in[DW-1:0];
out[DW-1:0] <= sync_reg0[DW-1:0];
end
endmodule // synchronizer
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/

10
parallella/fpga/parallella_base/parallella_base_ip.tcl
View File

@ -21,7 +21,7 @@ set hdl_files [list \
]
set ip_files [list \
$root/memory/ip/xilinx/fifo_async_104x32.xci \
$root/memory/fpga/fifo_async_104x32.xci \
]
set constraints_files []
@ -75,16 +75,16 @@ foreach file $ip_files {
###########################################################
# SYNTHESIZE (FOR SANITY)
###########################################################
set_property top $design [current_fileset]
launch_runs synth_1 -jobs 2
wait_on_run synth_1
#set_property top $design [current_fileset]
#launch_runs synth_1 -jobs 2
#wait_on_run synth_1
###########################################################
# Package
###########################################################
::ipx::package_project -import_files -force -root_dir $design
::ipx::package_project -import_files -force -root_dir $projdir
::set_property vendor {www.parallella.org} [ipx::current_core]
::set_property library {user} [ipx::current_core]
::set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]