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Removing reset
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@ -20,10 +20,7 @@ module pulse_stretcher (/*AUTOARG*/
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reg [DW-1:0] wide_pulse;
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reg [DW-1:0] wide_pulse;
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always @ (posedge clk or posedge reset)
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always @ (posedge clk)
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if(reset)
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wide_pulse[DW-1:0] <= 'b0;
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else
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wide_pulse[DW-1:0] <= {wide_pulse[DW-2:0],in};
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wide_pulse[DW-1:0] <= {wide_pulse[DW-2:0],in};
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assign out = (|{wide_pulse[DW-1:0],in});
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assign out = (|{wide_pulse[DW-1:0],in});
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