diff --git a/elink/dv/build.sh b/elink/dv/build.sh
index 19d472e..fa7a4ad 100755
--- a/elink/dv/build.sh
+++ b/elink/dv/build.sh
@@ -8,7 +8,7 @@
 #
 dut="elink"
 top="../../common/dv/dv_top.v"
-iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1  ../../memory/fpga/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v  ../../memory/fpga/sim/fifo_async_104x32.v  $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp
+iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp
 
 #PUT TARGET_SIM 
 
diff --git a/elink/dv/dut_axi_elink.v b/elink/dv/dut_axi_elink.v
index 015bb29..27b8d93 100644
--- a/elink/dv/dut_axi_elink.v
+++ b/elink/dv/dut_axi_elink.v
@@ -529,13 +529,14 @@ module dut(/*AUTOARG*/
    
 
    //"Arbitration" between read/write transaction   
-   assign  emem_access           = elink1_rxwr_access | elink1_rxrd_access;      
-
+   assign  emem_access           = ~elink1_rxwr_wait & (elink1_rxwr_access | elink1_rxrd_access);
+   
    assign  emem_packet[PW-1:0]   = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
                                                         elink1_rxrd_packet[PW-1:0];
 
-   assign elink1_rxrd_wait       = emem_wait | elink1_rxwr_access;
-   assign elink1_rxwr_wait       = 1'b0;//TODO: elink1_random_wait
+   assign elink1_rxrd_wait       = emem_wait | 
+				   elink1_rxwr_access |
+				   elink1_rxwr_wait;
    
    /*ememory AUTO_TEMPLATE ( 
                         // Outputs
@@ -559,6 +560,17 @@ module dut(/*AUTOARG*/
 		 .access_in		(emem_access),		 // Templated
 		 .packet_in		(emem_packet[PW-1:0]));	 // Templated
 
+
+   //Write wait circuit
+   reg [7:0] wait_counter;   
+   always @ (posedge clk or negedge nreset)
+     if(!nreset)
+       wait_counter[7:0] <= 'b0;   
+     else
+       wait_counter[7:0] <= wait_counter+1'b1;
+      
+   assign elink1_rxwr_wait       = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0;
+   
         
 endmodule // dv_elink
 // Local Variables:
diff --git a/elink/dv/dut_elink.v b/elink/dv/dut_elink.v
index 98f6721..6fc779b 100644
--- a/elink/dv/dut_elink.v
+++ b/elink/dv/dut_elink.v
@@ -313,14 +313,16 @@ module dut(/*AUTOARG*/
    wire emem_wait;
    
    //"Arbitration" between read/write transaction   
-   assign  emem_access           = elink1_rxwr_access | elink1_rxrd_access;      
+   assign  emem_access           = ~elink1_rxwr_wait & (elink1_rxwr_access | elink1_rxrd_access);      
 
    assign  emem_packet[PW-1:0]   = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
                                                         elink1_rxrd_packet[PW-1:0];
 
-   assign elink1_rxrd_wait       = emem_wait | elink1_rxwr_access;
+   assign elink1_rxrd_wait       = emem_wait | 
+				   elink1_rxwr_access |
+				   elink1_rxwr_wait;
+  
   
-   
    /*ememory AUTO_TEMPLATE ( 
                         // Outputs
                         .\(.*\)_out       (elink1_txrr_\1[]),
@@ -333,13 +335,14 @@ module dut(/*AUTOARG*/
 		 .clk		        (clk),
 		 .wait_out		(emem_wait),
 		 .coreid		(12'h0),
+		 .access_in		(emem_access),		 // Templated
 		 /*AUTOINST*/
 		 // Outputs
 		 .access_out		(elink1_txrr_access),	 // Templated
 		 .packet_out		(elink1_txrr_packet[PW-1:0]), // Templated
 		 // Inputs
 		 .nreset		(nreset),
-		 .access_in		(emem_access),		 // Templated
+		 
 		 .packet_in		(emem_packet[PW-1:0]));	 // Templated
 
 
@@ -351,7 +354,7 @@ module dut(/*AUTOARG*/
      else
        wait_counter[7:0] <= wait_counter+1'b1;
       
-   assign elink1_rxwr_wait       = 1'b0;//(|wait_counter[7:0]);//1'b0;
+   assign elink1_rxwr_wait       = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0;
    
 endmodule // dv_elink
 // Local Variables: