From 88dd3be734e28f24047c49cbdf441649dd7789a8 Mon Sep 17 00:00:00 2001 From: aolofsson Date: Mon, 2 Aug 2021 18:18:54 -0400 Subject: [PATCH] Creating mathlib for arithmetic --- asiclib/README.md | 4 +- {stdlib => mathlib}/hdl/oh_abs.v | 0 {stdlib => mathlib}/hdl/oh_add.v | 0 {stdlib => mathlib}/hdl/oh_bin2gray.v | 0 {stdlib => mathlib}/hdl/oh_bin2onehot.v | 0 {stdlib => mathlib}/hdl/oh_bitreverse.v | 0 {stdlib => mathlib}/hdl/oh_csa32.v | 0 {stdlib => mathlib}/hdl/oh_csa42.v | 0 {stdlib => mathlib}/hdl/oh_csa62.v | 0 {stdlib => mathlib}/hdl/oh_csa92.v | 0 {stdlib => mathlib}/hdl/oh_mult.v | 0 {stdlib => mathlib}/hdl/oh_shift.v | 0 stdlib/README.md | 65 ++----------------------- 13 files changed, 6 insertions(+), 63 deletions(-) rename {stdlib => mathlib}/hdl/oh_abs.v (100%) rename {stdlib => mathlib}/hdl/oh_add.v (100%) rename {stdlib => mathlib}/hdl/oh_bin2gray.v (100%) rename {stdlib => mathlib}/hdl/oh_bin2onehot.v (100%) rename {stdlib => mathlib}/hdl/oh_bitreverse.v (100%) rename {stdlib => mathlib}/hdl/oh_csa32.v (100%) rename {stdlib => mathlib}/hdl/oh_csa42.v (100%) rename {stdlib => mathlib}/hdl/oh_csa62.v (100%) rename {stdlib => mathlib}/hdl/oh_csa92.v (100%) rename {stdlib => mathlib}/hdl/oh_mult.v (100%) rename {stdlib => mathlib}/hdl/oh_shift.v (100%) diff --git a/asiclib/README.md b/asiclib/README.md index 011e004..3e94f7c 100644 --- a/asiclib/README.md +++ b/asiclib/README.md @@ -1,7 +1,7 @@ ASICLIB ===================================== -* ASICLIB is a library of low level "standard" cells hard-coded to a specific PDK. -* The hdl/*.v files represent the golden model for the library. Any hard coded library must implement the logical functionality exactly. +* ASICLIB is a library of low level asic cells hard-coded to a specific PDK. +* The hdl/*.v files represent the golden model for the library. A hard coded implementation must implement the logical functionality exactly. * The library is meant to be linked in at compile time based on the foundry being targeted. * The cells do not have any dependancies. diff --git a/stdlib/hdl/oh_abs.v b/mathlib/hdl/oh_abs.v similarity index 100% rename from stdlib/hdl/oh_abs.v rename to mathlib/hdl/oh_abs.v diff --git a/stdlib/hdl/oh_add.v b/mathlib/hdl/oh_add.v similarity index 100% rename from stdlib/hdl/oh_add.v rename to mathlib/hdl/oh_add.v diff --git a/stdlib/hdl/oh_bin2gray.v b/mathlib/hdl/oh_bin2gray.v similarity index 100% rename from stdlib/hdl/oh_bin2gray.v rename to mathlib/hdl/oh_bin2gray.v diff --git a/stdlib/hdl/oh_bin2onehot.v b/mathlib/hdl/oh_bin2onehot.v similarity index 100% rename from stdlib/hdl/oh_bin2onehot.v rename to mathlib/hdl/oh_bin2onehot.v diff --git a/stdlib/hdl/oh_bitreverse.v b/mathlib/hdl/oh_bitreverse.v similarity index 100% rename from stdlib/hdl/oh_bitreverse.v rename to mathlib/hdl/oh_bitreverse.v diff --git a/stdlib/hdl/oh_csa32.v b/mathlib/hdl/oh_csa32.v similarity index 100% rename from stdlib/hdl/oh_csa32.v rename to mathlib/hdl/oh_csa32.v diff --git a/stdlib/hdl/oh_csa42.v b/mathlib/hdl/oh_csa42.v similarity index 100% rename from stdlib/hdl/oh_csa42.v rename to mathlib/hdl/oh_csa42.v diff --git a/stdlib/hdl/oh_csa62.v b/mathlib/hdl/oh_csa62.v similarity index 100% rename from stdlib/hdl/oh_csa62.v rename to mathlib/hdl/oh_csa62.v diff --git a/stdlib/hdl/oh_csa92.v b/mathlib/hdl/oh_csa92.v similarity index 100% rename from stdlib/hdl/oh_csa92.v rename to mathlib/hdl/oh_csa92.v diff --git a/stdlib/hdl/oh_mult.v b/mathlib/hdl/oh_mult.v similarity index 100% rename from stdlib/hdl/oh_mult.v rename to mathlib/hdl/oh_mult.v diff --git a/stdlib/hdl/oh_shift.v b/mathlib/hdl/oh_shift.v similarity index 100% rename from stdlib/hdl/oh_shift.v rename to mathlib/hdl/oh_shift.v diff --git a/stdlib/README.md b/stdlib/README.md index 468e12b..5fac6da 100644 --- a/stdlib/README.md +++ b/stdlib/README.md @@ -1,63 +1,6 @@ -Common Module Library +STDLIB =============================================== -| Name |Done| Function | -|--------------------------------------------|:--:|--------------------------------| -| [oh_8b10b_decode](hdl/oh_8b10b_decode.v) | N | 8b10b decoder | -| [oh_8b10b_encode](hdl/oh_8b10b_encode.v) | N | 8b10b encoder | -| [oh_abs](hdl/oh_abs.v) | Y | Absolute value calculator | -| [oh_add](hdl/oh_add.v) | Y | Binary adder | -| [oh_arbiter](hdl/oh_arbiter.v) | Y | Configurable arbiter | -| [oh_bin2gray](hdl/oh_bin2gray.v) | Y | Binary to gray converter | -| [oh_bitreverse](hdl/oh_bitreverse.v) | Y | Bitreverse circuit | -| [oh_clockdiv](hdl/oh_clockdiv.v) | Y | Combinatorial clock divider | -| [oh_clockgate](hdl/oh_clockgate.v) | Y | Clock gater | -| [oh_counter](hdl/oh_counter.v) | Y | Binary counter | -| [oh_crc](hdl/oh_crc.v) | Y | CRC encoder | -| [oh_csa32](hdl/oh_csa32.v) | Y | Carry save adder 3:2 | -| [oh_csa42](hdl/oh_csa42.v) | Y | Carry save adder 4:2 | -| [oh_csa62](hdl/oh_csa62.v) | Y | Carry save adder 6:2 | -| [oh_csa92](hdl/oh_csa92.v) | Y | Carry save adder 9:2 | -| [oh_datagate](hdl/oh_datagate.v) | Y | Data gater | -| [oh_debouncer](hdl/oh_debouncer.v) | Y | Button debouncer | -| [oh_dsync](hdl/oh_dsync.v) | Y | Data synchronizizer | -| [oh_edge2pulse](hdl/oh_edge2pulse.v) | Y | Converts edge to pulse | -| [oh_edgealign](hdl/oh_edgealign.v) | Y | Fast/slow clock alignment | -| [oh_edgedetect](hdl/oh_edgedetect.v) | Y | Configurable edge detector | -| [oh_fall2pulse](hdl/oh_fall2pulse.v) | Y | Converts falling edge to pulse | -| [oh_fifo_async](hdl/oh_fifo_async.v) | Y | Asynchonous FIFO (dual clock) | -| [oh_fifo_cdc](hdl/oh_fifo_cdc.v) | Y | Clock domain crossing FIFO | -| [oh_fifo_generic](hdl/oh_fifo_generic.v) | Y | Generic synchronous FIFO | -| [oh_fifo_sync](hdl/oh_fifo_sync.v) | Y | Synchronous FIFO | -| [oh_gray2bin](hdl/oh_gray2bin.v) | Y | Gray to binary converter | -| [oh_iddr](hdl/oh_iddr.v) | Y | Dual data rate input buffer | -| [oh_lat0](hdl/oh_lat0.v) | Y | Latch on low clock | -| [oh_lat1](hdl/oh_lat1.v) | Y | latch on high clock | -| [oh_memory_dp](hdl/oh_memory_dp.v) | Y | Dual ported memory | -| [oh_memory_sp](hdl/oh_memory_sp.v) | Y | Single ported memory | -| [oh_mux12](hdl/oh_mux12.v) | Y | Twelve port mux | -| [oh_mux2](hdl/oh_mux2.v) | Y | Two port mux | -| [oh_mux3](hdl/oh_mux3.v) | Y | Three port mux | -| [oh_mux4](hdl/oh_mux4.v) | Y | Four port mux | -| [oh_mux5](hdl/oh_mux5.v) | Y | Five port mux | -| [oh_mux6](hdl/oh_mux6.v) | Y | Six port mux | -| [oh_mux7](hdl/oh_mux7.v) | Y | Seven port mux | -| [oh_mux8](hdl/oh_mux8.v) | Y | Eight port mux | -| [oh_mux9](hdl/oh_mux9.v) | Y | Ten port mux | -| [oh_mux](hdl/oh_mux.v) | Y | Generic n-port mux | -| [oh_oddr](hdl/oh_oddr.v) | Y | Dual data rate output buffer | -| [oh_par2ser](hdl/oh_par2ser.v) | Y | Parallel to serial converter | -| [oh_parity](hdl/oh_parity.v) | Y | Parity calculator | -| [oh_pulse2pulse](hdl/oh_pulse2pulse.v) | Y | Pulse to pulse CDC circuit | -| [oh_rise2pulse](hdl/oh_rise2pulse.v) | Y | Rising edge to pulse converter | -| [oh_rsync](hdl/oh_rsync.v) | Y | Reset synchronzation circuit | -| [oh_ser2par](hdl/oh_ser2par.v) | Y | Serial to parallel converter | -| [oh_shifter](hdl/oh_shifter.v) | Y | Bit shifter | -| [oh_standby](hdl/oh_standby.v) | Y | Standby circuit | -| [oh_stretcher](hdl/oh_stretcher.v) | Y | Pulse stretcher | - - - - - - +* STDLIB is a library of low level vectoried building blocks for control and datapath logic. +* Where appropriate, parameters are included to enable soft and hard-coded implementation. +* Some library cells call on others cells within the library