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Adding ASIC parameter to special library functions
- Needed to map to specific proprietary libraries - Need to hide actual cells behind abstraction due to NDA
This commit is contained in:
Andreas Olofsson
parent
3314051934
commit
8b24139be1
@ -5,7 +5,9 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_clockgate #(parameter DW = 1) // width of data
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module oh_clockgate #(parameter DW = 1, // width of data
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parameter ASIC = 0 // use ASIC lib
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)
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(
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input nrst, // active low sync reset (synced to input clk)
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input clk, // clock input
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@ -14,6 +16,7 @@ module oh_clockgate #(parameter DW = 1) // width of data
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output [DW-1:0] eclk// enabled clock output
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);
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wire [DW-1:0] en_sh;
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wire [DW-1:0] en_sl;
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@ -5,7 +5,8 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa32 #(parameter DW = 1 // data width
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module oh_csa32 #(parameter DW = 1, // data width
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parameter ASIC = 0 // use asic library
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)
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( input [DW-1:0] in0, //input
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input [DW-1:0] in1,//input
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@ -13,12 +14,25 @@ module oh_csa32 #(parameter DW = 1 // data width
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output [DW-1:0] s, //sum
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output [DW-1:0] c //carry
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);
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assign s[DW-1:0] = in0[DW-1:0] ^ in1[DW-1:0] ^ in2[DW-1:0];
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assign c[DW-1:0] = (in0[DW-1:0] & in1[DW-1:0]) |
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(in1[DW-1:0] & in2[DW-1:0]) |
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(in2[DW-1:0] & in0[DW-1:0] );
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generate
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if(ASIC)
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begin
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asic_csa32 i_csa32[DW-1:0] (.s(s[DW-1:0]),
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.c(c[DW-1:0]),
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.in2(in2[DW-1:0]),
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.in1(in1[DW-1:0]),
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.in0(in0[DW-1:0]));
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end
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else
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begin
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assign s[DW-1:0] = in0[DW-1:0] ^ in1[DW-1:0] ^ in2[DW-1:0];
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assign c[DW-1:0] = (in0[DW-1:0] & in1[DW-1:0]) |
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(in1[DW-1:0] & in2[DW-1:0]) |
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(in2[DW-1:0] & in0[DW-1:0] );
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end
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endgenerate
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endmodule // oh_csa32
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@ -5,7 +5,9 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa42 #( parameter DW = 1) // data width
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module oh_csa42 #( parameter DW = 1 , // data width
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parameter ASIC = 0 // use asic library
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)
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( input [DW-1:0] in0, //input
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input [DW-1:0] in1,//input
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input [DW-1:0] in2,//input
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@ -16,26 +18,42 @@ module oh_csa42 #( parameter DW = 1) // data width
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output [DW-1:0] cout //carry out
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);
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wire [DW-1:0] s_int;
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generate
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if(ASIC)
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begin
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asic_csa42 i_csa42[DW-1:0] (.s(s[DW-1:0]),
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.cout(cout[DW-1:0]),
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.c(c[DW-1:0]),
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.cin(cin[DW-1:0]),
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.in3(in3[DW-1:0]),
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.in2(in2[DW-1:0]),
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.in1(in1[DW-1:0]),
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.in0(in0[DW-1:0]));
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end
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else
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begin
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wire [DW-1:0] s_int;
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assign s[DW-1:0] = in0[DW-1:0] ^
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in1[DW-1:0] ^
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in2[DW-1:0] ^
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in3[DW-1:0] ^
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cin[DW-1:0];
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assign s_int[DW-1:0] = in1[DW-1:0] ^
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in2[DW-1:0] ^
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in3[DW-1:0];
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assign c[DW-1:0] = (in0[DW-1:0] & s_int[DW-1:0]) |
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(in0[DW-1:0] & cin[DW-1:0]) |
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(s_int[DW-1:0] & cin[DW-1:0]);
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assign cout[DW-1:0] = (in1[DW-1:0] & in2[DW-1:0]) |
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(in1[DW-1:0] & in3[DW-1:0]) |
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(in2[DW-1:0] & in3[DW-1:0]);
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end // else: !if(ASIC)
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endgenerate
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assign s[DW-1:0] = in0[DW-1:0] ^
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in1[DW-1:0] ^
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in2[DW-1:0] ^
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in3[DW-1:0] ^
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cin[DW-1:0];
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assign s_int[DW-1:0] = in1[DW-1:0] ^
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in2[DW-1:0] ^
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in3[DW-1:0];
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assign c[DW-1:0] = (in0[DW-1:0] & s_int[DW-1:0]) |
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(in0[DW-1:0] & cin[DW-1:0]) |
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(s_int[DW-1:0] & cin[DW-1:0]);
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assign cout[DW-1:0] = (in1[DW-1:0] & in2[DW-1:0]) |
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(in1[DW-1:0] & in3[DW-1:0]) |
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(in2[DW-1:0] & in3[DW-1:0]);
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endmodule // oh_csa42
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@ -5,8 +5,9 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_dsync #(parameter DW = 1, // width of data
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parameter PS = 3 // mnumber of sync stages
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module oh_dsync #(parameter DW = 1, // width of data
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parameter PS = 3, // mnumber of sync stages
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parameter ASIC = 0 // use asic library
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)
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(
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input clk, // clock
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@ -15,36 +16,43 @@ module oh_dsync #(parameter DW = 1, // width of data
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output [DW-1:0] dout // synchronized data
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);
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reg [DW-1:0] sync_pipe[PS:0]; //extra cycle for DV
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// variable length synchronizer pipe
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genvar i;
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generate
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for(i=0;i<(PS+1);i=i+1)
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if(i==0)
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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sync_pipe[0][DW-1:0] <= 'b0;
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else
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sync_pipe[0][DW-1:0] <= din[DW-1:0];
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else
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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sync_pipe[i][DW-1:0] <= 'b0;
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else
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sync_pipe[i][DW-1:0] <= sync_pipe[i-1][DW-1:0];
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endgenerate
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generate
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if(ASIC)
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begin
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asic_dsync #(.DW(DW))
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asic_dsync(.clk(clk),
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.nreset(nreset),
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.din(din[DW-1:0]),
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.dout(dout[DW-1:0]));
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end
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else
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begin
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reg [DW-1:0] sync_pipe[PS:0]; //extra cycle for DV
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genvar i;
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for(i=0;i<(PS+1);i=i+1)
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if(i==0)
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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sync_pipe[0][DW-1:0] <= 'b0;
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else
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sync_pipe[0][DW-1:0] <= din[DW-1:0];
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else
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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sync_pipe[i][DW-1:0] <= 'b0;
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else
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sync_pipe[i][DW-1:0] <= sync_pipe[i-1][DW-1:0];
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`ifdef TARGET_SIM
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// randomize sync delay based on value in per bit delay register
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// delay to be forced from testbench
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reg [DW-1:0] delay = 0;
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assign dout[DW-1:0] = (delay[DW-1:0] & sync_pipe[PS][DW-1:0]) | //extra cycle
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(~delay[DW-1:0] & sync_pipe[PS-1][DW-1:0]); //default
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// randomize sync delay based on value in per bit delay register
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// delay to be forced from testbench
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reg [DW-1:0] delay = 0;
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assign dout[DW-1:0] = (delay[DW-1:0] & sync_pipe[PS][DW-1:0]) | //extra cycle
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(~delay[DW-1:0] & sync_pipe[PS-1][DW-1:0]); //default
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`else
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assign dout[DW-1:0] = sync_pipe[PS-1][DW-1:0];
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assign dout[DW-1:0] = sync_pipe[PS-1][DW-1:0];
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`endif
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end
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endgenerate
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endmodule // oh_dsync
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@ -8,6 +8,7 @@
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module oh_memory_dp # (parameter DW = 104, //memory width
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parameter DEPTH = 32, //memory depth
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parameter PROJ = "", //project name
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parameter ASIC = 0, // use ASIC lib
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parameter MCW = 8, //repair/config vector width
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parameter AW = $clog2(DEPTH) // address bus width
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)
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@ -36,12 +37,12 @@ module oh_memory_dp # (parameter DW = 104, //memory width
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input [DW-1:0] bist_din // data input
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);
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`ifdef CFG_ASIC
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//NOT IMPLEMENTED...
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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oh_memory_ram (//read port
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generate
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if(ASIC)
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begin
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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i_sram (//read port
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.rd_dout (rd_dout[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (rd_en),
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@ -52,23 +53,25 @@ module oh_memory_dp # (parameter DW = 104, //memory width
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.wr_addr (wr_addr[AW-1:0]),
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.wr_wem (wr_wem[DW-1:0]),
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.wr_din (wr_din[DW-1:0]));
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`else
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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oh_memory_ram (//read port
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.rd_dout (rd_dout[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]),
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//write port
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.wr_en (wr_en),
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.wr_clk (wr_clk),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_wem (wr_wem[DW-1:0]),
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.wr_din (wr_din[DW-1:0]));
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`endif
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end // if (ASIC)
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else
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begin
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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oh_memory_ram (//read port
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.rd_dout (rd_dout[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (rd_en),
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.rd_addr (rd_addr[AW-1:0]),
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//write port
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.wr_en (wr_en),
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.wr_clk (wr_clk),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_wem (wr_wem[DW-1:0]),
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.wr_din (wr_din[DW-1:0]));
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end // else: !if(ASIC)
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endgenerate
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endmodule // oh_memory_dp
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@ -5,10 +5,11 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_memory_sp # (parameter DW = 104, //memory width
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parameter DEPTH = 32, //memory depth
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parameter PROJ = "", //project name
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parameter MCW = 8 //repair/config vector width
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module oh_memory_sp # (parameter DW = 104, // memory width
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parameter DEPTH = 32, // memory depth
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parameter PROJ = "", // project name
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parameter ASIC = 0, // use ASIC lib
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parameter MCW = 8 // repair/config vector width
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)
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(// memory interface (single port)
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input clk, // clock
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@ -35,51 +36,51 @@ module oh_memory_sp # (parameter DW = 104, //memory width
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parameter AW = $clog2(DEPTH); // address bus width
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`ifdef CFG_ASIC
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//Actual IP hidden behind wrapper to protect the innocent
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sram_sp #(.DW(DW),
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.DEPTH(DEPTH),
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.PROJ(PROJ),
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.MCW(MCW))
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sram_sp (// Outputs
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.dout (dout[DW-1:0]),
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// Inputs
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.clk (clk),
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.en (en),
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.we (we),
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.wem (wem[DW-1:0]),
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.addr (addr[AW-1:0]),
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.din (din[DW-1:0]),
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.vdd (vdd),
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.vddm (vddm),
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.vss (vss),
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.shutdown (shutdown),
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.memconfig (memconfig[MCW-1:0]),
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.memrepair (memrepair[MCW-1:0]),
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.bist_en (bist_en),
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.bist_we (bist_we),
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.bist_wem (bist_wem[DW-1:0]),
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.bist_addr (bist_addr[AW-1:0]),
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.bist_din (bist_din[DW-1:0]));
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`else
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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oh_memory_ram (//read port
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.rd_dout (dout[DW-1:0]),
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.rd_clk (clk),
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.rd_addr (addr[AW-1:0]),
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.rd_en (en & ~we),
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//write port
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.wr_clk (clk),
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.wr_en (en & we),
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.wr_addr (addr[AW-1:0]),
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.wr_wem (wem[DW-1:0]),
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.wr_din (din[DW-1:0]));
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`endif
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generate
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if(ASIC)
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begin
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asic_sram_sp #(.DW(DW),
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.DEPTH(DEPTH),
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.PROJ(PROJ),
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.MCW(MCW))
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i_sram (// Outputs
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.dout (dout[DW-1:0]),
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// Inputs
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.clk (clk),
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.en (en),
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.we (we),
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.wem (wem[DW-1:0]),
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.addr (addr[AW-1:0]),
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.din (din[DW-1:0]),
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.vdd (vdd),
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.vddm (vddm),
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.vss (vss),
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.shutdown (shutdown),
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.memconfig (memconfig[MCW-1:0]),
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.memrepair (memrepair[MCW-1:0]),
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.bist_en (bist_en),
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.bist_we (bist_we),
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.bist_wem (bist_wem[DW-1:0]),
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.bist_addr (bist_addr[AW-1:0]),
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.bist_din (bist_din[DW-1:0]));
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end
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else
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begin
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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oh_memory_ram (//read port
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.rd_dout (dout[DW-1:0]),
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.rd_clk (clk),
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.rd_addr (addr[AW-1:0]),
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.rd_en (en & ~we),
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//write port
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.wr_clk (clk),
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.wr_en (en & we),
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.wr_addr (addr[AW-1:0]),
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.wr_wem (wem[DW-1:0]),
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.wr_din (din[DW-1:0]));
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end
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endgenerate
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endmodule // oh_memory_sp
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@ -5,14 +5,25 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_pwr_gate (input npower, // active low power on
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input vdd, // input supply
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output vddg // gated output supply
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);
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module oh_pwr_gate #(parameter ASIC = 0 // use ASIC lib
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)
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(input npower, // active low power on
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input vdd, // input supply
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output vddg // gated output supply
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);
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`ifdef TARGET_SIM
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assign vddg = ((vdd===1'b1) && (npower===1'b0)) ? 1'b1 : 1'bX;
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`else
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generate
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if(ASIC)
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begin
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asic_pwr_header i_header (.npower(npower),
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.vdd(vdd),
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.vddg(vddg));
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end
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endgenerate
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`endif
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endmodule // oh_pwr_gate
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@ -5,20 +5,35 @@
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_pwr_isolate #(parameter DW = 1) // width of data inputs
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module oh_pwr_isolate #(parameter DW = 1, // width of data inputs
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parameter ASIC = 0 // use ASIC lib
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)
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(
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input vdd, // supply (set to 1 if valid)
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input vss, // ground (set to 0 if valid)
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input niso, // active low isolation signal
|
||||
input [DW-1:0] in, // input signal
|
||||
output [DW-1:0] out // buffered output signal
|
||||
input niso,// active low isolation signal
|
||||
input [DW-1:0] in, // input signal
|
||||
output [DW-1:0] out // buffered output signal
|
||||
);
|
||||
|
||||
|
||||
|
||||
`ifdef TARGET_SIM
|
||||
assign out[DW-1:0] = ((vdd===1'b1) && (vss===1'b0)) ? ({(DW){niso}} & in[DW-1:0]):
|
||||
{(DW){1'bX}};
|
||||
`else
|
||||
assign out[DW-1:0] = {(DW){niso}} & in[DW-1:0];
|
||||
generate
|
||||
if(ASIC)
|
||||
begin
|
||||
asic_iso i_iso [DW-1:0] (.vdd(vdd),
|
||||
.vss(vss),
|
||||
.in(in[DW-1:0]),
|
||||
.out(out[DW-1:0]));
|
||||
end
|
||||
else
|
||||
begin
|
||||
assign out[DW-1:0] = {(DW){niso}} & in[DW-1:0];
|
||||
end
|
||||
endgenerate
|
||||
`endif
|
||||
|
||||
endmodule // oh_buf
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user