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Fixing register file

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-Changing DW to RW (RW not always equal to DW..)
-Blocking rd_data on valid
-Fixing elemetary bugs based on indices
-Simplifying index code
-Add configurable pipeline stage?
This commit is contained in:
Andreas.Olofsson 2020-04-07 10:23:35 -04:00
parent 68829c93d0
commit 8b39f7e444
1 changed files with 18 additions and 14 deletions
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32
common/hdl/oh_regfile.v
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@ -5,43 +5,47 @@
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_regfile # (parameter DW = 64, // data width
parameter REGS = 32, // memory
module oh_regfile # (parameter REGS = 32, // number of registeres
parameter RW = 64, // register width
parameter RP = 5, // read ports
parameter WP = 5, // write prots
parameter AW = $clog2(REGS) // address width
parameter WP = 3 // write prots
)
(//Control inputs
input clk,
input nreset,
// Write Ports (concatenated)
input [WP-1:0] wr_valid, // write access
input [WP*AW-1:0] wr_addr, // register address
input [WP*DW-1:0] wr_data, // write data
input [WP*RAW-1:0] wr_addr, // register address
input [WP*RW-1:0] wr_data, // write data
// Read Ports (concatenated)
input [RP-1:0] rd_valid, // read access
input [RP*AW-1:0] rd_addr, // register address
output [RP*DW-1:0] rd_data // output data
input [RP*RAW-1:0] rd_addr, // register address
output [RP*RW-1:0] rd_data // output data
);
genvar i;
localparam RAW = $clog2(REGS);
genvar i;
reg [DW-1:0] mem [0:REGS-1];
reg [RW-1:0] mem [0:REGS-1];
//TODO: Make an array of cells
//#########################################
// write port
// write ports
//#########################################
for (i=0;i<RP;i=i+1)
for (i=0;i<WP;i=i+1)
always @ (posedge clk)
if (wr_valid[i])
mem[wr_addr[(i+1)*AW-1:i*AW]] <= wr_data[(i+1)*DW-1:i*DW];
mem[wr_addr[(i+1)*RAW-1:i*RAW]] <= wr_data[(i+1)*RW-1:i*RW];
//#########################################
// read ports
//#########################################
for (i=0;i<RP;i=i+1)
assign rd_data[(i+1)*DW-1:i*DW] = mem[rd_addr[(i+1)*AW-1:i*AW]];
assign rd_data[i*RW+:RW] = {(RW){rd_valid[i]}} &
mem[rd_addr[i*RAW+:RAW]];
endmodule // oh_regfile