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Clean axi_elink module
-Clocks included inside for easy integration -Another version might have the clocks and reset as inputs instead
This commit is contained in:
Andreas Olofsson
parent
6d9731f14a
commit
8d3cbf8257
@ -1,31 +1,30 @@
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module axi_elink(/*AUTOARG*/
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// Outputs
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rx_lclk_div4, tx_lclk_div4, rxo_wr_wait_p, rxo_wr_wait_n,
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rxo_rd_wait_p, rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p,
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txo_frame_n, txo_data_p, txo_data_n, chipid, chip_resetb, cclk_p,
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cclk_n, mailbox_not_empty, mailbox_full, timeout, m_axi_awid,
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m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
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m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
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m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
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m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
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m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
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m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
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s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
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s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
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s_axi_wready,
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, chipid, chip_resetb, cclk_p, cclk_n, mailbox_not_empty,
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mailbox_full, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
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m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot,
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m_axi_awqos, m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb,
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m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
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m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock,
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m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid,
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m_axi_rready, s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp,
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s_axi_bvalid, s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp,
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s_axi_rvalid, s_axi_wready,
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// Inputs
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reset, pll_clk, sys_clk, testmode, rxi_lclk_p, rxi_lclk_n,
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rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p,
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txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, m_axi_aresetn,
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m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
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m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast,
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m_axi_rvalid, s_axi_aresetn, s_axi_arid, s_axi_araddr,
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s_axi_arburst, s_axi_arcache, s_axi_arlock, s_axi_arlen,
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s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid,
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s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awlock,
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s_axi_awlen, s_axi_awprot, s_axi_awqos, s_axi_awsize,
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s_axi_awvalid, s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata,
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s_axi_wlast, s_axi_wstrb, s_axi_wvalid
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reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
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rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, m_axi_aresetn, m_axi_awready,
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m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_arready,
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m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
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s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
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s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
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s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
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s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
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s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
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s_axi_wstrb, s_axi_wvalid
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);
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parameter AW = 32;
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@ -34,22 +33,17 @@ module axi_elink(/*AUTOARG*/
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parameter ID = 12'h810;
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parameter IDW = 12; //ID width for AXI
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/****************************/
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/*CLK AND RESET */
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/****************************/
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input reset; // active high async reset
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input pll_clk; // pll input clock
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input sys_clk; // system clock for FIFOs only
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input testmode; // places elink in testmode
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output rx_lclk_div4; // rx clock for synching with logic
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output tx_lclk_div4; // tx clock for synching with logic
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input sys_clk; // system clock for AXI
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/********************************/
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/*ELINK I/O PINS */
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/********************************/
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//Receiver
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_frame_p, rxi_frame_n; //link rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; //link rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
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@ -67,7 +61,7 @@ module axi_elink(/*AUTOARG*/
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/********************************/
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output [11:0] chipid; //chip id strap pins for Epiphany
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output chip_resetb; //chip reset for Epiphany (active low)
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output cclk_p, cclk_n; //high speed clock (up to 1GHz) to Epiphany
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output cclk_p,cclk_n; //high speed clock (up to 1GHz) to Epiphany
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/*****************************/
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/*MAILBOX (interrupts) */
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@ -75,11 +69,6 @@ module axi_elink(/*AUTOARG*/
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output mailbox_not_empty;
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output mailbox_full;
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/*****************************/
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/*READBACK TIMEOUT */
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/*****************************/
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output timeout;
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//########################
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//AXI MASTER INTERFACE
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//########################
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@ -193,12 +182,17 @@ module axi_elink(/*AUTOARG*/
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire elink_en; // From elink of elink.v
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wire elink_reset; // From eclocks of eclocks.v
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wire rx_lclk; // From eclocks of eclocks.v
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wire rx_lclk_div4; // From eclocks of eclocks.v
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wire rx_lclk_pll; // From elink of elink.v
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wire rx_ref_clk; // From eclocks of eclocks.v
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wire rxrd_access; // From elink of elink.v
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wire [PW-1:0] rxrd_packet; // From elink of elink.v
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wire rxrd_wait; // From emaxi of emaxi.v
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@ -208,6 +202,10 @@ module axi_elink(/*AUTOARG*/
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wire rxwr_access; // From elink of elink.v
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wire [PW-1:0] rxwr_packet; // From elink of elink.v
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wire rxwr_wait; // From emaxi of emaxi.v
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wire timeout; // From elink of elink.v
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wire tx_lclk; // From eclocks of eclocks.v
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wire tx_lclk90; // From eclocks of eclocks.v
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wire tx_lclk_div4; // From eclocks of eclocks.v
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wire txrd_access; // From esaxi of esaxi.v
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wire [PW-1:0] txrd_packet; // From esaxi of esaxi.v
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wire txrd_wait; // From elink of elink.v
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@ -220,7 +218,93 @@ module axi_elink(/*AUTOARG*/
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// End of automatics
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//AXI SLAVE INTERFACE
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//########################################################
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//ELINK
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//########################################################
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elink elink(.reset (elink_reset),
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/*AUTOINST*/
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// Outputs
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.rx_lclk_pll (rx_lclk_pll),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.chipid (chipid[11:0]),
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.elink_en (elink_en),
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.mailbox_not_empty (mailbox_not_empty),
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.mailbox_full (mailbox_full),
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.timeout (timeout),
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// Inputs
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.sys_clk (sys_clk),
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]));
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//########################################################
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//CLOCK AND RESET
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//########################################################
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eclocks eclocks (.rx_clkin (rx_lclk_pll),
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/*AUTOINST*/
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// Outputs
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.elink_reset (elink_reset),
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.chip_resetb (chip_resetb),
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// Inputs
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.reset (reset),
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.elink_en (elink_en),
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.sys_clk (sys_clk));
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//########################################################
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//AXI SLAVE
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//########################################################
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esaxi esaxi (.s_axi_aclk (sys_clk),
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/*AUTOINST*/
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// Outputs
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@ -274,7 +358,10 @@ module axi_elink(/*AUTOARG*/
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.s_axi_wstrb (s_axi_wstrb[3:0]),
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.s_axi_wvalid (s_axi_wvalid));
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//AXI MASTET INTERFACE
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//########################################################
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//AXI MASTER INTERFACE
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//########################################################
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emaxi emaxi (.m_axi_aclk (sys_clk),
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/*AUTOINST*/
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// Outputs
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@ -328,61 +415,6 @@ module axi_elink(/*AUTOARG*/
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.m_axi_rlast (m_axi_rlast),
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.m_axi_rvalid (m_axi_rvalid));
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//ELINK
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elink elink(/*AUTOINST*/
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// Outputs
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.rx_lclk_div4 (rx_lclk_div4),
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.tx_lclk_div4 (tx_lclk_div4),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.chipid (chipid[11:0]),
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.chip_resetb (chip_resetb),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.mailbox_not_empty (mailbox_not_empty),
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.mailbox_full (mailbox_full),
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.timeout (timeout),
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// Inputs
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.reset (reset),
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.pll_clk (pll_clk),
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.sys_clk (sys_clk),
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.testmode (testmode),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]));
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endmodule // elink
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// Local Variables:
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