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Copyright cleanup

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This commit is contained in:
Andreas Olofsson 2015-08-07 09:19:37 -04:00
parent 617e5f76de
commit 8e32299f2c
9 changed files with 15 additions and 17 deletions
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14
elink/hdl/axi_elink.v
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@ -31,9 +31,9 @@ module axi_elink(/*AUTOARG*/
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
parameter IOSTD_ELINK = "LVDS_25";
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
parameter IOSTD_ELINK = "LVDS_25";
/****************************/
/*CLK AND RESET */
@ -77,7 +77,7 @@ module axi_elink(/*AUTOARG*/
input m_axi_aresetn; // global reset singal.
//Write address channel
output [M_IDW-1:0] m_axi_awid; // write address ID
output [M_IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
@ -98,13 +98,13 @@ module axi_elink(/*AUTOARG*/
input m_axi_wready; // slave is ready for data
//Write response channel
input [M_IDW-1:0] m_axi_bid;
input [M_IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [M_IDW-1:0] m_axi_arid; // read address ID
output [M_IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
@ -427,7 +427,7 @@ endmodule // elink
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>

2
elink/hdl/eclocks.v
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@ -391,7 +391,7 @@ endmodule // eclocks
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
Contributed by Gunnar Hillerstrom

2
elink/hdl/elink.v
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@ -285,7 +285,7 @@ endmodule // elink
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>

2
elink/hdl/ereset.v
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@ -53,7 +53,7 @@ endmodule // ereset
// verilog-library-directories:("." "../../common/hdl/")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>

2
elink/hdl/erx_cfg.v
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@ -136,7 +136,7 @@ module erx_cfg (/*AUTOARG*/
endmodule // ecfg_rx
/*
Copyright (C) 2013 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify

2
elink/hdl/erx_fifo.v
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@ -139,7 +139,7 @@ endmodule // erx
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>

4
elink/hdl/erx_protocol.v
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@ -68,9 +68,7 @@ endmodule // erx_protocol
// End:
/*
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify

2
elink/hdl/esaxi.v
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@ -489,7 +489,7 @@ module esaxi (/*autoarg*/
endmodule // esaxi
/*
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
Contributed by Fred Huettig <fred@adapteva.com>

2
elink/hdl/etx_protocol.v
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@ -155,7 +155,7 @@ endmodule // etx_protocol
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify