From 971b59145497240762ac101ca5327692b2d458fb Mon Sep 17 00:00:00 2001
From: Andreas Olofsson <andreas@adapteva.com>
Date: Mon, 2 Nov 2015 20:51:35 -0500
Subject: [PATCH] Shifting first byte of packet down by one bit to accomodate
 new format - this of for future proofing

---
 elink/hdl/erx_arbiter.v  |  4 ++--
 elink/hdl/erx_io.v       |  1 -
 elink/hdl/erx_protocol.v |  7 ++++---
 elink/hdl/etx_arbiter.v  | 13 ++++++-------
 elink/hdl/etx_io.v       |  7 +++++++
 5 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/elink/hdl/erx_arbiter.v b/elink/hdl/erx_arbiter.v
index 28fd74c..62a13d7 100644
--- a/elink/hdl/erx_arbiter.v
+++ b/elink/hdl/erx_arbiter.v
@@ -79,9 +79,9 @@ module erx_arbiter (/*AUTOARG*/
    assign ecfg_wait           = erx_rr_access;
 
    //####################################
-   //Write Path (direct)
+   //Write Path (through MMU)
    //####################################
-   assign emmu_write          = emmu_packet[1];
+   assign emmu_write          = emmu_packet[0];
 
    assign rxwr_access         = emmu_access & emmu_write;
    
diff --git a/elink/hdl/erx_io.v b/elink/hdl/erx_io.v
index e65a311..11083e4 100644
--- a/elink/hdl/erx_io.v
+++ b/elink/hdl/erx_io.v
@@ -2,7 +2,6 @@
  This block receives the IO transaction and converts to a 104 bit packet. 
  */
 
-`include "elink_constants.v"
 module erx_io (/*AUTOARG*/
    // Outputs
    rx_clkin, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
diff --git a/elink/hdl/erx_protocol.v b/elink/hdl/erx_protocol.v
index 576f245..4007789 100644
--- a/elink/hdl/erx_protocol.v
+++ b/elink/hdl/erx_protocol.v
@@ -3,6 +3,7 @@
  read responses
  */
 `include "elink_regmap.v"
+
 module erx_protocol (/*AUTOARG*/
    // Outputs
    erx_test_access, erx_test_data, erx_rdwr_access, erx_rr_access,
@@ -15,7 +16,6 @@ module erx_protocol (/*AUTOARG*/
    parameter DW   = 32;
    parameter PW   = 104;
    parameter ID   = 12'h800; //link id
-
    
    // System reset input
    input           clk;
@@ -69,6 +69,7 @@ module erx_protocol (/*AUTOARG*/
       
    
    //Pipeline stage and decode  
+   
    always @ (posedge clk)
      begin
 	  //Write/read request
@@ -80,8 +81,8 @@ module erx_protocol (/*AUTOARG*/
 	  //Common packet
 	  erx_packet[PW-1:0]  <= {rx_packet[PW-1:40],
 				  dstaddr_mux[31:0],
-				  rx_packet[7:0]
-				  };
+				  {1'b0,rx_packet[7:1]} //NOTE: remvoing redundant access packet bit
+				  };                    //This is to conform to new format	 
      end
 
    //Testdata to write
diff --git a/elink/hdl/etx_arbiter.v b/elink/hdl/etx_arbiter.v
index ccbf72f..ebe32bb 100644
--- a/elink/hdl/etx_arbiter.v
+++ b/elink/hdl/etx_arbiter.v
@@ -81,18 +81,17 @@ module etx_arbiter (/*AUTOARG*/
    wire            write_in;
 
    //##########################################################################
-   //# Insert special control mode
+   //# Insert special control mode in packet
    //##########################################################################
    assign txrd_ctrlmode[3:0] =  ctrlmode_bypass ?  ctrlmode[3:0] : 
-				                   txrd_packet[7:4];
+				                   txrd_packet[6:3];
+     
+   assign txwr_ctrlmode[3:0] =  ctrlmode_bypass ?  ctrlmode[3:0] : 
+				                   txwr_packet[6:3];
 
    assign txrd_data[PW-1:0] = {txrd_packet[PW-1:8],   
                                txrd_ctrlmode[3:0], 
 			       txrd_packet[3:0]};
- 
-   
-   assign txwr_ctrlmode[3:0] =  ctrlmode_bypass ?  ctrlmode[3:0] : 
-				                   txwr_packet[7:4];
 
    assign txwr_data[PW-1:0] = {txwr_packet[PW-1:8],   
                                txwr_ctrlmode[3:0], 
@@ -169,7 +168,7 @@ module etx_arbiter (/*AUTOARG*/
    
 endmodule // etx_arbiter
 // Local Variables:
-// verilog-library-directories:("." "../../common/hdl")
+// verilog-library-directories:("." "../../emesh/hdl")
 // End:
 
 
diff --git a/elink/hdl/etx_io.v b/elink/hdl/etx_io.v
index 6090e94..932650f 100644
--- a/elink/hdl/etx_io.v
+++ b/elink/hdl/etx_io.v
@@ -128,6 +128,13 @@ always @ (posedge tx_lclk)
 		      .srcaddr_out	(srcaddr[31:0]),
 		      .packet_in	(tx_packet_reg[PW-1:0]));
  
+
+   /*
+    * The following format is used by the Epiphany multicore ASIC.
+    * Don't change it if you want to communicate with Epiphany.
+    * 
+    */
+
    always @ (posedge tx_lclk)
      if (tx_new_frame)
        tx_double[63:0] <= {16'b0,//16