diff --git a/common/fpga/system_build.tcl b/common/fpga/system_build.tcl index 158cddc..cdaf23d 100644 --- a/common/fpga/system_build.tcl +++ b/common/fpga/system_build.tcl @@ -8,6 +8,7 @@ make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/syste ########################################################### # Add generated wrapper file ########################################################### +remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ########################################################### diff --git a/common/fpga/system_init.tcl b/common/fpga/system_init.tcl index 0a8177f..f466bd0 100644 --- a/common/fpga/system_init.tcl +++ b/common/fpga/system_init.tcl @@ -1,8 +1,6 @@ ########################################################### # OH! Specific constants ########################################################### -set report_dir $projdir/reports -set results_dir $projdir/results ########################################################### # CREATE PROJECT @@ -13,6 +11,8 @@ set_property target_language Verilog [current_project] ########################################################### # Create Report/Results Directory ########################################################### +set report_dir $projdir/reports +set results_dir $projdir/results if ![file exists $report_dir] {file mkdir $report_dir} if ![file exists $results_dir] {file mkdir $results_dir} @@ -50,11 +50,11 @@ if {[llength $hdl_files] != 0} { } #CONSTRAINTS -if {[string equal [get_filesets -quiet constraints_1] ""]} { - create_fileset -constrset constraints_1 +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 } if {[llength $constraints_files] != 0} { - add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files + add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files }