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Future proof emesh format with another byte of controls

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-At 144 bits, it's less than 5% in signals and virtually no power penalty
-The goal is to be completely axi feature compliant
This commit is contained in:
Andreas.Olofsson 2020-09-21 09:20:22 -04:00
parent 89f995c20c
commit 98b7494678
2 changed files with 33 additions and 16 deletions
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14
emesh/hdl/emesh2packet.v
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@ -10,7 +10,7 @@ module emesh2packet #(parameter AW = 32, // address width
//Emesh signal bundle
input write_out,
input [1:0] datamode_out,
input [4:0] ctrlmode_out,
input [12:0] ctrlmode_out,
input [AW-1:0] dstaddr_out,
input [AW-1:0] data_out,
input [AW-1:0] srcaddr_out,
@ -38,8 +38,16 @@ module emesh2packet #(parameter AW = 32, // address width
assign packet_out[2:1] = datamode_out[1:0];
assign packet_out[7:3] = ctrlmode_out[4:0];
generate
if(PW==136)
generate
if(PW==144)
begin : p144
assign packet_out[39:8] = dstaddr_out[31:0];
assign packet_out[71:40] = data_out[31:0]; // | srcaddr_out[63:32]
assign packet_out[103:72] = srcaddr_out[31:0]; // (data_out[63:32])
assign packet_out[135:104] = dstaddr_out[63:32];
assign packet_out[143:136] = ctrlmode_out[12:5];
end
else if(PW==136)
begin : p136
assign packet_out[39:8] = dstaddr_out[31:0];
assign packet_out[71:40] = data_out[31:0]; // | srcaddr_out[63:32]

35
emesh/hdl/packet2emesh.v
View File

@ -10,9 +10,9 @@ module packet2emesh #(parameter AW = 32, // address width
//Input packet
input [PW-1:0] packet_in,
//Emesh signal bundle
output write_in, // write signal
output write_in, // write signal
output [1:0] datamode_in,// datasize
output [4:0] ctrlmode_in,// ctrlmode
output [12:0] ctrlmode_in,// ctrlmode
output [AW-1:0] dstaddr_in, // read/write address
output [AW-1:0] srcaddr_in, // return address for reads
output [AW-1:0] data_in // data
@ -35,29 +35,38 @@ module packet2emesh #(parameter AW = 32, // address width
// [135:104] dstaddr(hi)
generate
if(PW==104)
begin : p104
assign write_in = packet_in[0];
assign datamode_in[1:0] = packet_in[2:1];
assign ctrlmode_in[4:0] = {1'b0,packet_in[6:3]};
assign dstaddr_in[31:0] = packet_in[39:8];
assign srcaddr_in[31:0] = packet_in[103:72];
assign data_in[31:0] = packet_in[71:40];
if(PW==144)
begin : p144
assign write_in = packet_in[0];
assign datamode_in[1:0] = packet_in[2:1];
assign ctrlmode_in[12:0] = {packet_in[143:136], packet_in[7:3]};
assign dstaddr_in[63:0] = {packet_in[135:104],packet_in[39:8]};
assign srcaddr_in[63:0] = {packet_in[71:40],packet_in[135:72]};
assign data_in[63:0] = packet_in[103:40];
end
else if(PW==136)
begin : p136
assign write_in = packet_in[0];
assign datamode_in[1:0] = packet_in[2:1];
assign ctrlmode_in[4:0] = packet_in[7:3];
assign ctrlmode_in[12:0] = {8'b0, packet_in[7:3]};
assign dstaddr_in[63:0] = {packet_in[135:104],packet_in[39:8]};
assign srcaddr_in[63:0] = {packet_in[71:40],packet_in[135:72]};
assign data_in[63:0] = packet_in[103:40];
end
else if(PW==104)
begin : p104
assign write_in = packet_in[0];
assign datamode_in[1:0] = packet_in[2:1];
assign ctrlmode_in[12:0] = {9'b0,packet_in[6:3]};
assign dstaddr_in[31:0] = packet_in[39:8];
assign srcaddr_in[31:0] = packet_in[103:72];
assign data_in[31:0] = packet_in[71:40];
end
else if(PW==72)
begin : p72
assign write_in = packet_in[0];
assign datamode_in[1:0] = packet_in[2:1];
assign ctrlmode_in[4:0] = packet_in[7:3];
assign ctrlmode_in[12:0] = {8'b0, packet_in[7:3]};
assign dstaddr_in[31:0] = packet_in[39:8];
assign data_in[31:0] = packet_in[71:40];
end
@ -65,7 +74,7 @@ module packet2emesh #(parameter AW = 32, // address width
begin : p40
assign write_in = packet_in[0];
assign datamode_in[1:0] = packet_in[2:1];
assign ctrlmode_in[4:0] = packet_in[7:3];
assign ctrlmode_in[12:0] = {8'b0, packet_in[7:3]};
assign dstaddr_in[15:0] = packet_in[23:8];
assign data_in[15:0] = packet_in[39:24];
end