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Adding testbench for stimulus
-New name, new methodology
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aolofsson
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@ -1,143 +1,141 @@
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// A stimulus file provides inputs signals to the design under test (DUT).
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// This stimulus module is designed to be compatible with verilog simulators,
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// emulators, and FPGA prototyping. This is akin to a simple test vector generator
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// No looping supported!
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//
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// Memory format:
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// b0 = valid,
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// b1-7 = wait time
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// b8-bxxx = packet
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//
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// Test Process:
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// 1. Zero out memory (or write program)
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// 2. Set go signal
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//
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module stimulus #( parameter DW = 32, // Memory width=DW+
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parameter MAW = 15, // Memory address width
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parameter HEXFILE = "NONE" // Name of hex file
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)
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(
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//Asynchronous Stimulus Reset
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input nreset,
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input ext_start, // Start driving stimulus
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input use_timestamps,//b1-7 used for timestamps
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input ignore_valid,//b0 valid bit ignored
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//External Load port
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input ext_clk,// External clock for write path
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input ext_access, // Valid packet for memory
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input [DW-1:0] ext_packet, // Packet for memory
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//DUT Drive port
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input dut_clk, // DUT side clock
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input dut_wait, // DUT stall signal
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output stim_access, // Access signal
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output [DW-1:0] stim_packet, // Packet
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output stim_done // Stimulus program done
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);
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// 3. Drive out all valid packets sequentially
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localparam MD = 1<<MAW; // Memory depth
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//Registers
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reg [DW-1:0] ram[0:MD-1];
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reg [1:0] rd_state;
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reg [MAW-1:0] wr_addr;
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reg [MAW-1:0] rd_addr;
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reg [255:0] memhfile;
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reg [1:0] sync_pipe;
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reg [6:0] rd_delay;
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reg [DW-1:0] stim_packet;
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reg stim_read;
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module stimulus
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#(parameter DW = 64, // Stimulus packet width
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parameter DEPTH = 1024, // Memory depth
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parameter CW = 0, // bit[0]=valid, [CW-1:1]=timestamp
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parameter MW = DW + CW, // Memory width (derived)
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parameter FILENAME = "NONE" // Simulus hexfile for $readmemh
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)
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(
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// External stimulus load port
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input nreset, // async reset
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input ext_start, // Start driving stimulus
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input ext_clk,// External clock for write path
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input ext_access, // Valid packet for memory
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input [MW-1:0] ext_packet, // Packet for memory
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// DUT drive port
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input dut_clk, // DUT side clock
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input dut_ready, // DUT ready signal
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output stim_valid, // Packet valid
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output [DW-1:0] stim_packet, // Packet data
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output stim_done // Signals that stimulus is done
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);
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// memory parameters
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parameter MAW = $clog2(DEPTH); // Memory address width
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// state machine parameters
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localparam STIM_IDLE = 2'b00;
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localparam STIM_ACTIVE = 2'b01;
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localparam STIM_PAUSE = 2'b10;
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localparam STIM_DONE = 2'b11;
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// Local values
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reg [MW-1:0] ram[0:DEPTH-1];
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reg [1:0] rd_state;
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reg [MAW-1:0] wr_addr;
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reg [MAW-1:0] rd_addr;
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reg [1:0] sync_pipe;
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reg mem_read;
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reg [MW-1:0] mem_data;
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reg [CW:0] rd_delay;
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wire dut_start;
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wire valid_packet;
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//#################################
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// Init memory if configured
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//#################################
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generate
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if(!(HEXFILE=="NONE"))
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if(!(FILENAME=="NONE"))
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initial
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begin
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$display("Initializing STIMULUS from %s", HEXFILE);
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$readmemh(HEXFILE, ram);
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$display("Driving stimulus from %s", FILENAME);
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$readmemh(FILENAME, ram);
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end
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endgenerate
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//#################################
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// Write port state machine
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//#################################
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always @ (posedge ext_clk or negedge nreset)
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if(!nreset)
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wr_addr[MAW-1:0] <= 'b0;
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wr_addr[MAW-1:0] <= 'b0;
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else if(ext_access)
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wr_addr[MAW-1:0] <= wr_addr[MAW-1:0] + 1;
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//Synchronize ext_start to dut_clk domain
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always @ (posedge dut_clk or negedge nreset)
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wr_addr[MAW-1:0] <= wr_addr[MAW-1:0] + 1;
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//Synchronize ext_start to dut_clk domain
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always @ (posedge dut_clk or negedge nreset)
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if(!nreset)
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sync_pipe[1:0] <= 1'b0;
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sync_pipe[1:0] <= 'b0;
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else
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sync_pipe[1:0] <= {sync_pipe[0],ext_start};
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sync_pipe[1:0] <= {sync_pipe[0],ext_start};
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assign dut_start = sync_pipe[1];
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//#################################
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// Read port state machine
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//#################################
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//1. Start on dut_start
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//2. After thar update rd state machine on all not stall and not wait
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//3. Set end state on special end packet
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//2. Drive stimulus while dut is ready
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//3. Set end state on special end packet (bit 0)
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`define STIM_IDLE 2'b00
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`define STIM_ACTIVE 2'b01
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`define STIM_PAUSE 2'b10
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`define STIM_DONE 2'b11
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always @ (posedge dut_clk or negedge nreset)
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if(!nreset)
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begin
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rd_state[1:0] <= `STIM_IDLE;
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rd_addr[MAW-1:0] <= 'b0;
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rd_delay[6:0] <= 'b0;
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rd_state[1:0] <= STIM_IDLE;
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rd_addr[MAW-1:0] <= 'b0;
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rd_delay <= 'b0;
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end
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else if(~dut_wait)
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else if(dut_ready)
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case (rd_state[1:0])
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`STIM_IDLE :
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rd_state[1:0] <= dut_start ? `STIM_ACTIVE : `STIM_IDLE;
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`STIM_ACTIVE :
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STIM_IDLE :
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rd_state[1:0] <= dut_start ? STIM_ACTIVE : STIM_IDLE;
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STIM_ACTIVE :
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begin
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rd_state[1:0] <= (|rd_delay[6:0]) ? `STIM_PAUSE :
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~stim_valid ? `STIM_DONE :
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`STIM_ACTIVE;
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rd_state[1:0] <= (|rd_delay) ? STIM_PAUSE :
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~stim_valid ? STIM_DONE :
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STIM_ACTIVE;
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rd_addr[MAW-1:0] <= rd_addr[MAW-1:0] + 1'b1;
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rd_delay[6:0] <= {(7){use_timestamps}} & stim_packet[7:1];
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rd_delay <= (CW > 1) ? mem_data[CW:1] : 'b0;
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end
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`STIM_PAUSE :
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STIM_PAUSE :
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begin
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rd_state[1:0] <= (|rd_delay[6:0]) ? `STIM_PAUSE : `STIM_ACTIVE;
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rd_delay[6:0] <= rd_delay[6:0] - 1'b1;
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rd_state[1:0] <= (|rd_delay) ? STIM_PAUSE : STIM_ACTIVE;
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rd_delay <= rd_delay - 1'b1;
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end
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endcase // case (rd_state[1:0])
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//Output Driver
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assign stim_done = (rd_state[1:0] == `STIM_DONE);
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assign stim_valid = ignore_valid | stim_packet[0];
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assign stim_done = (rd_state[1:0] == STIM_DONE);
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assign valid_packet = (CW==0) | mem_data[0];
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//#################################
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// RAM
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//#################################
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//write port
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always @(posedge ext_clk)
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always @(posedge ext_clk)
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if(ext_access)
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ram[wr_addr[MAW-1:0]] <= ext_packet[DW-1:0];
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ram[wr_addr[MAW-1:0]] <= ext_packet[MW-1:0];
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//read port
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always @ (posedge dut_clk)
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begin
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stim_packet[DW-1:0] <= ram[rd_addr[MAW-1:0]];
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stim_read <= (rd_state==`STIM_ACTIVE); //mem-cycle adjust
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mem_data[MW-1:0] <= ram[rd_addr[MAW-1:0]];
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mem_read <= (rd_state==STIM_ACTIVE); //mem-cycle adjust
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end
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//Shut off access immediately, but pipeline delay by one cycle
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assign stim_access = stim_valid & stim_read & ~stim_done;
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endmodule // stimulus
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assign stim_valid = valid_packet & mem_read & ~stim_done;
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assign stim_packet[DW-1:0] = mem_data[MW-1:CW];
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endmodule // stimulus
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52
src/stdlib/dv/tb_oh_stimulus.v
Normal file
52
src/stdlib/dv/tb_oh_stimulus.v
Normal file
@ -0,0 +1,52 @@
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module testbench();
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localparam DW = 144;
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localparam CW = 8;
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localparam FILENAME = "test.mem"; //
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire nreset; // From oh_simctrl of oh_simctrl.v
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wire start; // From oh_simctrl of oh_simctrl.v
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wire stim_done; // From oh_stimulus of oh_stimulus.v
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wire [DW-1:0] stim_packet; // From oh_stimulus of oh_stimulus.v
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wire stim_valid; // From oh_stimulus of oh_stimulus.v
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wire vdd; // From oh_simctrl of oh_simctrl.v
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wire vss; // From oh_simctrl of oh_simctrl.v
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// End of automatics
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oh_stimulus #(.DW(DW),
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.CW(CW),
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.FILENAME(FILENAME))
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oh_stimulus(.dut_ready (1'b1),
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.dut_clk (dut_clk),
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.ext_valid (1'b0),
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.ext_packet ({(DW + CW){1'b0}}),
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.ext_clk (ext_clk),
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.ext_start (start),
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/*AUTOINST*/
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// Outputs
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.stim_valid (stim_valid),
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.stim_packet (stim_packet[DW-1:0]),
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.stim_done (stim_done),
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// Inputs
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.nreset (nreset));
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oh_simctrl oh_simctrl(.stim_done (1'b0),
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.test_done (1'b1),
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.test_diff (1'b0),
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.dut_active (1'b1),
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.clk1 (ext_clk),
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.clk2 (dut_clk),
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/*AUTOINST*/
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// Outputs
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.nreset (nreset),
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.start (start),
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.vdd (vdd),
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.vss (vss));
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endmodule // tb
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// Local Variables:
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// verilog-library-directories:("." "../hdl")
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// End:
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