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Fixed elink platform compile errors

Browse Source 
-Ultrascale changes broke the zynq design
-Adding CFG_PLATFORM variable to control compilation target
This commit is contained in:
Andreas Olofsson 2017-11-22 11:32:20 -05:00
parent 8cc0809580
commit 998f3021cc
4 changed files with 334 additions and 225 deletions
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1
scripts/build.sh
View File

@ -22,6 +22,7 @@ $OH_HOME/scripts/link.sh
iverilog -g2005\
-DTARGET_SIM=1\
-DCFG_ASIC=0\
-DCFG_PLATFORM=\"ZYNQ\"\
$DUT\
$OH_HOME/symlinks/dv/dv_top.v\
-y .\

220
src/elink/hdl/erx_io.v
View File

@ -2,6 +2,7 @@
This block receives the IO transaction and converts to a 104 bit packet.
*/
module erx_io (/*AUTOARG*/
// Outputs
rx_clkin, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
@ -11,6 +12,7 @@ module erx_io (/*AUTOARG*/
rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
rxi_data_n, rx_wr_wait, rx_rd_wait
);
parameter PLATFORM = `CFG_PLATFORM;
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
@ -309,89 +311,159 @@ module erx_io (/*AUTOARG*/
//###################################
assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
//Taking care of Xilinx generation incompatibilty issues %#$@!!
genvar j;
generate for(j=0; j<9; j=j+1)
begin : gen_idelay
generate
if(PLATFORM=="ULTRASCALE")
begin : ultrascale
for(j=0; j<9; j=j+1)
begin : gen_idelay
`define IDELAYCTRL_WONT_SYNTHESIZE
`ifdef IDELAYCTRL_WONT_SYNTHESIZE
IDELAYE3 #(.DELAY_SRC("IDATAIN"),
.DELAY_TYPE("VAR_LOAD"),
.DELAY_VALUE(9'b0),
.REFCLK_FREQUENCY(200.0),
.DELAY_FORMAT("COUNT"), // Ultrascale w/ COUNT can remove IDELAYCTRL (but then not stable over temp / voltage variations)
.SIM_DEVICE("ULTRASCALE_PLUS_ES2"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.CLK(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CNTVALUEIN({4'b0, idelay_value[(j+1)*5-1:j*5]}), //variable tap (BROKEN!!! for Ultrascale, 9 bits / counter
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LOAD(load_taps), // load new
.EN_VTC(~load_taps), // Enables IDELAYCTRL
.RST(1'b0) //
);
IDELAYE3 #(.DELAY_SRC("IDATAIN"),
.DELAY_TYPE("VAR_LOAD"),
.DELAY_VALUE(9'b0),
.REFCLK_FREQUENCY(200.0),
.DELAY_FORMAT("COUNT"), // Ultrascale w/ COUNT can remove IDELAYCTRL (but then not stable over temp / voltage variations)
.SIM_DEVICE("ULTRASCALE_PLUS_ES2"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.CLK(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CNTVALUEIN({4'b0, idelay_value[(j+1)*5-1:j*5]}), //variable tap (BROKEN!!! for Ultrascale, 9 bits / counter
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LOAD(load_taps), // load new
.EN_VTC(~load_taps), // Enables IDELAYCTRL
.RST(1'b0) //
);
`else
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE3 #(.DELAY_SRC("IDATAIN"),
.DELAY_TYPE("VAR_LOAD"),
.DELAY_VALUE(9'b0),
.REFCLK_FREQUENCY(200.0),
.DELAY_FORMAT("TIME"), // Ultrascale w/ COUNT can remove IDELAYCTRL (but then not stable over temp / voltage variations)
.SIM_DEVICE("ULTRASCALE_PLUS_ES2"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.CLK(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CNTVALUEIN({4'b0, idelay_value[(j+1)*5-1:j*5]}), //variable tap (BROKEN!!! for Ultrascale, 9 bits / counter
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LOAD(load_taps), // load new
.EN_VTC(~load_taps), // Enables IDELAYCTRL
.RST(1'b0) //
);
`endif
end // block: gen_idelay
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE3 #(.DELAY_SRC("IDATAIN"),
.DELAY_TYPE("VAR_LOAD"),
.DELAY_VALUE(9'b0),
.REFCLK_FREQUENCY(200.0),
.DELAY_FORMAT("TIME"), // Ultrascale w/ COUNT can remove IDELAYCTRL (but then not stable over temp / voltage variations)
.SIM_DEVICE("ULTRASCALE_PLUS_ES2"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.CLK(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CNTVALUEIN({4'b0, idelay_value[(j+1)*5-1:j*5]}), //variable tap (BROKEN!!! for Ultrascale, 9 bits / counter
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LOAD(load_taps), // load new
.EN_VTC(~load_taps), // Enables IDELAYCTRL
.RST(1'b0) //
);
`endif // !`ifdef IDELAYCTRL_WONT_SYNTHESIZE
end // block: gen_idelay
end // block: ultrascale
else
begin: zynq
genvar j;
for(j=0; j<9; j=j+1)
begin : gen_idelay
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.IDELAY_TYPE("VAR_LOAD"),
.IDELAY_VALUE(5'b0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.C(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CINVCTRL(1'b0), // inverts clock polarity
.CNTVALUEIN(idelay_value[(j+1)*5-1:j*5]), //variable tap
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LD(load_taps), // load new
.LDPIPEEN(1'b0), // only for pipeline mode
.REGRST(1'b0)); // only for pipeline mode
end // block: gen_idelay
end // block: zynq
endgenerate
//#############################
//# IDDR SAMPLERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_iddr
// Ultrascale doesn't have .SRTYPE("SYNC")
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
iddr_data (
.Q1 (rx_word_iddr[i]),
.Q2 (rx_word_iddr[i+8]),
.C (rx_lclk_iddr),//rx_lclk_iddr
.CB (~rx_lclk_iddr),
.D (rxi_delay_out[i] ^ invert_pins),
.R (1'b0)
);
end
endgenerate
//FRAME
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
// Ultrascale doesn't have .SRTYPE("SYNC")
iddr_frame (
.Q1 (rx_frame_iddr),
.Q2 (),
.C (rx_lclk_iddr),//TODO: will this work?
.CB (~rx_lclk_iddr),
.D (rxi_delay_out[8] ^ invert_pins),
.R (1'b0)
);
generate
genvar i;
if(PLATFORM=="ULTRASCALE")
begin : gen_ultrascale
//DATA
for(i=0; i<8; i=i+1)
begin : gen_iddr
// Ultrascale doesn't have .SRTYPE("SYNC")
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
iddr_data (
.Q1 (rx_word_iddr[i]),
.Q2 (rx_word_iddr[i+8]),
.C (rx_lclk_iddr),//rx_lclk_iddr
.CB (~rx_lclk_iddr),
.D (rxi_delay_out[i] ^ invert_pins),
.R (1'b0)
);
end
//FRAME
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
// Ultrascale doesn't have .SRTYPE("SYNC")
iddr_frame (
.Q1 (rx_frame_iddr),
.Q2 (),
.C (rx_lclk_iddr),//TODO: will this work?
.CB (~rx_lclk_iddr),
.D (rxi_delay_out[8] ^ invert_pins),
.R (1'b0)
);
end // block: ultrascale
else
begin : gen_zynq
// DATA
for(i=0; i<8; i=i+1)
begin : gen_iddr
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_data (
.Q1 (rx_word_iddr[i]),
.Q2 (rx_word_iddr[i+8]),
.C (rx_lclk_iddr),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[i] ^ invert_pins),
.R (1'b0),
.S (1'b0));
end // block: gen_iddr
//FRAME
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_frame (
.Q1 (rx_frame_iddr),
.Q2 (),
.C (rx_lclk_iddr),//TODO: will this work?
.CE (1'b1),
.D (rxi_delay_out[8] ^ invert_pins),
.R (1'b0),
.S (1'b0)
);
end // block: zynq
endgenerate
endmodule // erx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")

216
src/elink/hdl/etx_clocks.v
View File

@ -7,15 +7,14 @@ module etx_clocks (/*AUTOARG*/
sys_nreset, soft_reset, sys_clk
);
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_TXCLK = 300;
parameter FREQ_CCLK = 600;
parameter TXCLK_PHASE = 90; //txclk phase shift
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
parameter PLATFORM = `CFG_PLATFORM;
//Override reset counter size for simulation
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
@ -173,105 +172,117 @@ module etx_clocks (/*AUTOARG*/
generate
if(TARGET=="XILINX")
begin
//###########################
// MMCM FOR TXCLK + CCLK
//###########################
MMCME2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(MMCM_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(SYSCLK_PERIOD),
.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), //cclk_c
.CLKOUT1_DIVIDE(TXCLK_DIVIDE), //tx_lclk
.CLKOUT2_DIVIDE(TXCLK_DIVIDE), //tx_lclk90
.CLKOUT3_DIVIDE(TXCLK_DIVIDE*4), //tx_lclk_div4
.CLKOUT4_DIVIDE(128), //N/A
.CLKOUT5_DIVIDE(128), //N/A
.CLKOUT6_DIVIDE(128), //N/A
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(TXCLK_PHASE),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) mmcm_cclk
(
.CLKOUT0(cclk_mmcm),
.CLKOUT0B(),
.CLKOUT1(tx_lclk_mmcm),
.CLKOUT1B(),
.CLKOUT2(tx_lclk90_mmcm),//goes directly to IO
.CLKOUT2B(),
.CLKOUT3(tx_lclk_div4_mmcm),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.PWRDWN(1'b0),
.RST(mmcm_reset), //reset
.CLKFBIN(cclk_fb),
.CLKFBOUT(cclk_fb), //feedback clock
.CLKFBOUTB(), //inverted output feedback clock
.CLKIN1(sys_clk), //input clock
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(mmcm_locked), //locked indicator
.PSCLK(1'b0),
.PSEN(1'b0),
.PSDONE(),
.PSINCDEC(1'b0),
.CLKFBSTOPPED(),
.CLKINSTOPPED()
);
//###########################
// MMCM FOR TXCLK + CCLK
//###########################
MMCME2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(MMCM_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(SYSCLK_PERIOD),
.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), //cclk_c
.CLKOUT1_DIVIDE(TXCLK_DIVIDE), //tx_lclk
.CLKOUT2_DIVIDE(TXCLK_DIVIDE), //tx_lclk90
.CLKOUT3_DIVIDE(TXCLK_DIVIDE*4), //tx_lclk_div4
.CLKOUT4_DIVIDE(128), //N/A
.CLKOUT5_DIVIDE(128), //N/A
.CLKOUT6_DIVIDE(128), //N/A
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(TXCLK_PHASE),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) mmcm_cclk
(
.CLKOUT0(cclk_mmcm),
.CLKOUT0B(),
.CLKOUT1(tx_lclk_mmcm),
.CLKOUT1B(),
.CLKOUT2(tx_lclk90_mmcm),//goes directly to IO
.CLKOUT2B(),
.CLKOUT3(tx_lclk_div4_mmcm),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.PWRDWN(1'b0),
.RST(mmcm_reset), //reset
.CLKFBIN(cclk_fb),
.CLKFBOUT(cclk_fb), //feedback clock
.CLKFBOUTB(), //inverted output feedback clock
.CLKIN1(sys_clk), //input clock
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(mmcm_locked), //locked indicator
.PSCLK(1'b0),
.PSEN(1'b0),
.PSDONE(),
.PSINCDEC(1'b0),
.CLKFBSTOPPED(),
.CLKINSTOPPED()
);
//Tx clock buffers
BUFG i_lclk_bufg (.I(tx_lclk_mmcm), .O(tx_lclk_io)); //300MHz
BUFG i_lclk_div4_bufg (.I(tx_lclk_div4_mmcm),.O(tx_lclk_div4)); //75MHz
BUFG i_lclk90_bufg (.I(tx_lclk90_mmcm), .O(tx_lclk90)); //300MHz 90deg clock
// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
//###########################
// CCLK
//###########################
//CCLK bufio
BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_mmcm));
//CCLK oddr
ODDRE1
oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.D1 (1'b1),
.D2 (1'b0));
//CCLK differential buffer
OBUFDS cclk_obuf (.O (cclk_p),
.OB (cclk_n),
.I (cclk_oddr)
);
//Tx clock buffers
BUFG i_lclk_bufg (.I(tx_lclk_mmcm), .O(tx_lclk_io)); //300MHz
BUFG i_lclk_div4_bufg (.I(tx_lclk_div4_mmcm),.O(tx_lclk_div4)); //75MHz
BUFG i_lclk90_bufg (.I(tx_lclk90_mmcm), .O(tx_lclk90)); //300MHz 90deg clock
// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
//###########################
// CCLK
//###########################
//CCLK bufio
BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_mmcm));
//CCLK oddr
if(PLATFORM=="ULTRASCALE")
begin : gen_ultrascale
ODDRE1 oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.D1 (1'b1),
.D2 (1'b0));
end
else
begin : gen_zynq
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
//CCLK differential buffer
OBUFDS cclk_obuf (.O (cclk_p),
.OB (cclk_n),
.I (cclk_oddr)
);
end // if (TARGET=="XILINX")
else
begin
@ -282,11 +293,6 @@ module etx_clocks (/*AUTOARG*/
assign tx_lclk90 = sys_clk;
end
endgenerate
endmodule // eclocks
// Local Variables:

122
src/elink/hdl/etx_io.v
View File

@ -7,6 +7,7 @@ module etx_io (/*AUTOARG*/
txi_rd_wait_p, txi_rd_wait_n, tx_data_slow, tx_frame_slow
);
parameter PLATFORM = `CFG_PLATFORM;
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 0; // 0 = parallella
@ -118,55 +119,84 @@ module etx_io (/*AUTOARG*/
//############################################
//# IO DRIVER STUFF
//############################################
generate
genvar i;
if(PLATFORM=="ULTRASCALE")
begin : ultrascale
//DATA
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDRE1 oddr_data (.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins));
end
//FRAME
ODDRE1 oddr_frame (.Q (txo_frame_ddr),
.C (tx_lclk_io),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins));
//LCLK
ODDRE1 oddr_lclk (.Q (txo_lclk90),
.C (tx_lclk90),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins));
end // block: ultrascale
else
begin : zynq
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins),
.R (1'b0),
.S (1'b0)
);
end
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_frame (
.Q (txo_frame_ddr),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
end
endgenerate
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDRE1
oddr_data (
.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins)
);
end
endgenerate
//FRAME
ODDRE1
oddr_frame (
.Q (txo_frame_ddr),
.C (tx_lclk_io),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins)
);
//LCLK
ODDRE1
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins)
);
//Buffer drivers
OBUFDS obufds_data[7:0] (
.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data_ddr[7:0])
);
OBUFDS obufds_data[7:0] (.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data_ddr[7:0]));
OBUFDS obufds_frame ( .O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame_ddr)
);
OBUFDS obufds_lclk ( .O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90)
);
OBUFDS obufds_frame (.O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame_ddr));
OBUFDS obufds_lclk (.O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90));
//Wait inputs
generate
if(ETYPE==1)