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Fixed elink platform compile errors

-Ultrascale changes broke the zynq design
-Adding CFG_PLATFORM variable to control compilation target
This commit is contained in:
Andreas Olofsson 2017-11-22 11:32:20 -05:00
parent 8cc0809580
commit 998f3021cc
4 changed files with 334 additions and 225 deletions

View File

@ -22,6 +22,7 @@ $OH_HOME/scripts/link.sh
iverilog -g2005\
-DTARGET_SIM=1\
-DCFG_ASIC=0\
-DCFG_PLATFORM=\"ZYNQ\"\
$DUT\
$OH_HOME/symlinks/dv/dv_top.v\
-y .\

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@ -2,6 +2,7 @@
This block receives the IO transaction and converts to a 104 bit packet.
*/
module erx_io (/*AUTOARG*/
// Outputs
rx_clkin, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
@ -11,6 +12,7 @@ module erx_io (/*AUTOARG*/
rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
rxi_data_n, rx_wr_wait, rx_rd_wait
);
parameter PLATFORM = `CFG_PLATFORM;
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
@ -310,8 +312,13 @@ module erx_io (/*AUTOARG*/
assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
genvar j;
generate for(j=0; j<9; j=j+1)
//Taking care of Xilinx generation incompatibilty issues %#$@!!
generate
if(PLATFORM=="ULTRASCALE")
begin : ultrascale
for(j=0; j<9; j=j+1)
begin : gen_idelay
`define IDELAYCTRL_WONT_SYNTHESIZE
`ifdef IDELAYCTRL_WONT_SYNTHESIZE
@ -355,17 +362,51 @@ module erx_io (/*AUTOARG*/
.EN_VTC(~load_taps), // Enables IDELAYCTRL
.RST(1'b0) //
);
`endif
`endif // !`ifdef IDELAYCTRL_WONT_SYNTHESIZE
end // block: gen_idelay
end // block: ultrascale
else
begin: zynq
genvar j;
for(j=0; j<9; j=j+1)
begin : gen_idelay
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.IDELAY_TYPE("VAR_LOAD"),
.IDELAY_VALUE(5'b0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.C(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CINVCTRL(1'b0), // inverts clock polarity
.CNTVALUEIN(idelay_value[(j+1)*5-1:j*5]), //variable tap
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LD(load_taps), // load new
.LDPIPEEN(1'b0), // only for pipeline mode
.REGRST(1'b0)); // only for pipeline mode
end // block: gen_idelay
end // block: zynq
endgenerate
//#############################
//# IDDR SAMPLERS
//#############################
//DATA
generate
genvar i;
generate for(i=0; i<8; i=i+1)
if(PLATFORM=="ULTRASCALE")
begin : gen_ultrascale
//DATA
for(i=0; i<8; i=i+1)
begin : gen_iddr
// Ultrascale doesn't have .SRTYPE("SYNC")
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
@ -378,7 +419,6 @@ module erx_io (/*AUTOARG*/
.R (1'b0)
);
end
endgenerate
//FRAME
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
@ -391,6 +431,38 @@ module erx_io (/*AUTOARG*/
.D (rxi_delay_out[8] ^ invert_pins),
.R (1'b0)
);
end // block: ultrascale
else
begin : gen_zynq
// DATA
for(i=0; i<8; i=i+1)
begin : gen_iddr
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_data (
.Q1 (rx_word_iddr[i]),
.Q2 (rx_word_iddr[i+8]),
.C (rx_lclk_iddr),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[i] ^ invert_pins),
.R (1'b0),
.S (1'b0));
end // block: gen_iddr
//FRAME
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_frame (
.Q1 (rx_frame_iddr),
.Q2 (),
.C (rx_lclk_iddr),//TODO: will this work?
.CE (1'b1),
.D (rxi_delay_out[8] ^ invert_pins),
.R (1'b0),
.S (1'b0)
);
end // block: zynq
endgenerate
endmodule // erx_io
// Local Variables:

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@ -7,14 +7,13 @@ module etx_clocks (/*AUTOARG*/
sys_nreset, soft_reset, sys_clk
);
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_TXCLK = 300;
parameter FREQ_CCLK = 600;
parameter TXCLK_PHASE = 90; //txclk phase shift
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
parameter PLATFORM = `CFG_PLATFORM;
//Override reset counter size for simulation
`ifdef TARGET_SIM
@ -173,7 +172,6 @@ module etx_clocks (/*AUTOARG*/
generate
if(TARGET=="XILINX")
begin
//###########################
// MMCM FOR TXCLK + CCLK
//###########################
@ -244,12 +242,11 @@ module etx_clocks (/*AUTOARG*/
.CLKINSTOPPED()
);
//Tx clock buffers
BUFG i_lclk_bufg (.I(tx_lclk_mmcm), .O(tx_lclk_io)); //300MHz
BUFG i_lclk_div4_bufg (.I(tx_lclk_div4_mmcm),.O(tx_lclk_div4)); //75MHz
BUFG i_lclk90_bufg (.I(tx_lclk90_mmcm), .O(tx_lclk90)); //300MHz 90deg clock
// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
//###########################
// CCLK
@ -259,12 +256,26 @@ module etx_clocks (/*AUTOARG*/
BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_mmcm));
//CCLK oddr
ODDRE1
oddr_lclk (
if(PLATFORM=="ULTRASCALE")
begin : gen_ultrascale
ODDRE1 oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.D1 (1'b1),
.D2 (1'b0));
end
else
begin : gen_zynq
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
end
//CCLK differential buffer
OBUFDS cclk_obuf (.O (cclk_p),
@ -283,11 +294,6 @@ module etx_clocks (/*AUTOARG*/
end
endgenerate
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")

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@ -7,6 +7,7 @@ module etx_io (/*AUTOARG*/
txi_rd_wait_p, txi_rd_wait_n, tx_data_slow, tx_frame_slow
);
parameter PLATFORM = `CFG_PLATFORM;
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 0; // 0 = parallella
@ -118,55 +119,84 @@ module etx_io (/*AUTOARG*/
//############################################
//# IO DRIVER STUFF
//############################################
//DATA
generate
genvar i;
generate for(i=0; i<8; i=i+1)
if(PLATFORM=="ULTRASCALE")
begin : ultrascale
//DATA
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDRE1
ODDRE1 oddr_data (.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins));
end
//FRAME
ODDRE1 oddr_frame (.Q (txo_frame_ddr),
.C (tx_lclk_io),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins));
//LCLK
ODDRE1 oddr_lclk (.Q (txo_lclk90),
.C (tx_lclk90),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins));
end // block: ultrascale
else
begin : zynq
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins)
.D2 (tx_data16[i] ^ invert_pins),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
ODDRE1
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_frame (
.Q (txo_frame_ddr),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins)
.D2 (tx_frame16 ^ invert_pins),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDRE1
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins)
.D2 (1'b0 ^ invert_pins),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
end
endgenerate
//Buffer drivers
OBUFDS obufds_data[7:0] (
.O (txo_data_p[7:0]),
OBUFDS obufds_data[7:0] (.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data_ddr[7:0])
);
.I (txo_data_ddr[7:0]));
OBUFDS obufds_frame ( .O (txo_frame_p),
OBUFDS obufds_frame (.O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame_ddr)
);
.I (txo_frame_ddr));
OBUFDS obufds_lclk ( .O (txo_lclk_p),
OBUFDS obufds_lclk (.O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90)
);
.I (txo_lclk90));
//Wait inputs
generate
if(ETYPE==1)