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https://github.com/aolofsson/oh.git
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Fixed elink platform compile errors
-Ultrascale changes broke the zynq design -Adding CFG_PLATFORM variable to control compilation target
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8cc0809580
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@ -22,6 +22,7 @@ $OH_HOME/scripts/link.sh
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iverilog -g2005\
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-DTARGET_SIM=1\
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-DCFG_ASIC=0\
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-DCFG_PLATFORM=\"ZYNQ\"\
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$DUT\
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$OH_HOME/symlinks/dv/dv_top.v\
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-y .\
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@ -2,6 +2,7 @@
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This block receives the IO transaction and converts to a 104 bit packet.
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*/
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module erx_io (/*AUTOARG*/
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// Outputs
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rx_clkin, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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@ -11,6 +12,7 @@ module erx_io (/*AUTOARG*/
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rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
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rxi_data_n, rx_wr_wait, rx_rd_wait
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);
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parameter PLATFORM = `CFG_PLATFORM;
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parameter IOSTD_ELINK = "LVDS_25";
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parameter PW = 104;
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parameter ETYPE = 1;//0=parallella
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@ -310,8 +312,13 @@ module erx_io (/*AUTOARG*/
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assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
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genvar j;
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generate for(j=0; j<9; j=j+1)
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//Taking care of Xilinx generation incompatibilty issues %#$@!!
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generate
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if(PLATFORM=="ULTRASCALE")
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begin : ultrascale
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for(j=0; j<9; j=j+1)
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begin : gen_idelay
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`define IDELAYCTRL_WONT_SYNTHESIZE
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`ifdef IDELAYCTRL_WONT_SYNTHESIZE
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@ -355,17 +362,51 @@ module erx_io (/*AUTOARG*/
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.EN_VTC(~load_taps), // Enables IDELAYCTRL
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.RST(1'b0) //
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);
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`endif
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`endif // !`ifdef IDELAYCTRL_WONT_SYNTHESIZE
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end // block: gen_idelay
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end // block: ultrascale
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else
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begin: zynq
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genvar j;
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for(j=0; j<9; j=j+1)
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begin : gen_idelay
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(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
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IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
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.DELAY_SRC("IDATAIN"),
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.HIGH_PERFORMANCE_MODE("FALSE"),
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.IDELAY_TYPE("VAR_LOAD"),
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.IDELAY_VALUE(5'b0),
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.PIPE_SEL("FALSE"),
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.REFCLK_FREQUENCY(200.0),
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.SIGNAL_PATTERN("DATA"))
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idelay_inst (.CNTVALUEOUT(), // monitoring value
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.DATAOUT(rxi_delay_out[j]), // delayed data
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.C(rx_lclk_div4), // variable tap delay clock
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.CE(1'b0), // inc/dec tap value
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.CINVCTRL(1'b0), // inverts clock polarity
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.CNTVALUEIN(idelay_value[(j+1)*5-1:j*5]), //variable tap
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.DATAIN(1'b0), // data from FPGA
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.IDATAIN(rxi_delay_in[j]), // data from ibuf
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.INC(1'b0), // increment tap
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.LD(load_taps), // load new
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.LDPIPEEN(1'b0), // only for pipeline mode
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.REGRST(1'b0)); // only for pipeline mode
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end // block: gen_idelay
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end // block: zynq
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endgenerate
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//#############################
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//# IDDR SAMPLERS
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//#############################
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//DATA
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generate
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genvar i;
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generate for(i=0; i<8; i=i+1)
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if(PLATFORM=="ULTRASCALE")
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begin : gen_ultrascale
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//DATA
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for(i=0; i<8; i=i+1)
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begin : gen_iddr
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// Ultrascale doesn't have .SRTYPE("SYNC")
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IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
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@ -378,7 +419,6 @@ module erx_io (/*AUTOARG*/
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.R (1'b0)
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);
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end
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endgenerate
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//FRAME
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IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
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@ -391,6 +431,38 @@ module erx_io (/*AUTOARG*/
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.D (rxi_delay_out[8] ^ invert_pins),
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.R (1'b0)
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);
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end // block: ultrascale
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else
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begin : gen_zynq
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// DATA
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for(i=0; i<8; i=i+1)
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begin : gen_iddr
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IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
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iddr_data (
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.Q1 (rx_word_iddr[i]),
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.Q2 (rx_word_iddr[i+8]),
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.C (rx_lclk_iddr),//rx_lclk_iddr
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.CE (1'b1),
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.D (rxi_delay_out[i] ^ invert_pins),
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.R (1'b0),
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.S (1'b0));
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end // block: gen_iddr
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//FRAME
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IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
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iddr_frame (
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.Q1 (rx_frame_iddr),
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.Q2 (),
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.C (rx_lclk_iddr),//TODO: will this work?
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.CE (1'b1),
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.D (rxi_delay_out[8] ^ invert_pins),
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.R (1'b0),
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.S (1'b0)
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);
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end // block: zynq
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endgenerate
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endmodule // erx_io
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// Local Variables:
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@ -7,14 +7,13 @@ module etx_clocks (/*AUTOARG*/
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sys_nreset, soft_reset, sys_clk
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);
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//Frequency Settings (Mhz)
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parameter FREQ_SYSCLK = 100;
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parameter FREQ_TXCLK = 300;
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parameter FREQ_CCLK = 600;
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parameter TXCLK_PHASE = 90; //txclk phase shift
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parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
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parameter PLATFORM = `CFG_PLATFORM;
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//Override reset counter size for simulation
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`ifdef TARGET_SIM
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@ -173,7 +172,6 @@ module etx_clocks (/*AUTOARG*/
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generate
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if(TARGET=="XILINX")
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begin
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//###########################
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// MMCM FOR TXCLK + CCLK
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//###########################
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@ -244,12 +242,11 @@ module etx_clocks (/*AUTOARG*/
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.CLKINSTOPPED()
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);
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//Tx clock buffers
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BUFG i_lclk_bufg (.I(tx_lclk_mmcm), .O(tx_lclk_io)); //300MHz
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BUFG i_lclk_div4_bufg (.I(tx_lclk_div4_mmcm),.O(tx_lclk_div4)); //75MHz
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BUFG i_lclk90_bufg (.I(tx_lclk90_mmcm), .O(tx_lclk90)); //300MHz 90deg clock
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// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
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// BUFG i_fb_buf (.I(cclk_fb_out), .O(cclk_fb_in)); //FB
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//###########################
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// CCLK
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@ -259,12 +256,26 @@ module etx_clocks (/*AUTOARG*/
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BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_mmcm));
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//CCLK oddr
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ODDRE1
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oddr_lclk (
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if(PLATFORM=="ULTRASCALE")
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begin : gen_ultrascale
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ODDRE1 oddr_lclk (
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.Q (cclk_oddr),
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.C (cclk_bufio),
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.D1 (1'b1),
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.D2 (1'b0));
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end
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else
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begin : gen_zynq
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
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oddr_lclk (
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.Q (cclk_oddr),
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.C (cclk_bufio),
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.CE (1'b1),
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.D1 (1'b1),
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.D2 (1'b0),
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.R (1'b0),
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.S (1'b0));
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end
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//CCLK differential buffer
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OBUFDS cclk_obuf (.O (cclk_p),
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@ -283,11 +294,6 @@ module etx_clocks (/*AUTOARG*/
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end
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endgenerate
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endmodule // eclocks
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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@ -7,6 +7,7 @@ module etx_io (/*AUTOARG*/
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txi_rd_wait_p, txi_rd_wait_n, tx_data_slow, tx_frame_slow
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);
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parameter PLATFORM = `CFG_PLATFORM;
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parameter IOSTD_ELINK = "LVDS_25";
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parameter PW = 104;
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parameter ETYPE = 0; // 0 = parallella
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@ -118,55 +119,84 @@ module etx_io (/*AUTOARG*/
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//############################################
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//# IO DRIVER STUFF
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//############################################
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//DATA
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generate
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genvar i;
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generate for(i=0; i<8; i=i+1)
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if(PLATFORM=="ULTRASCALE")
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begin : ultrascale
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//DATA
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for(i=0; i<8; i=i+1)
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begin : gen_oddr
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ODDRE1
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ODDRE1 oddr_data (.Q (txo_data_ddr[i]),
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.C (tx_lclk_io),
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.D1 (tx_data16[i+8] ^ invert_pins),
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.D2 (tx_data16[i] ^ invert_pins));
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end
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//FRAME
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ODDRE1 oddr_frame (.Q (txo_frame_ddr),
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.C (tx_lclk_io),
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.D1 (tx_frame16 ^ invert_pins),
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.D2 (tx_frame16 ^ invert_pins));
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//LCLK
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ODDRE1 oddr_lclk (.Q (txo_lclk90),
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.C (tx_lclk90),
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.D1 (1'b1 ^ invert_pins),
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.D2 (1'b0 ^ invert_pins));
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end // block: ultrascale
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else
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begin : zynq
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for(i=0; i<8; i=i+1)
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begin : gen_oddr
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
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oddr_data (
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.Q (txo_data_ddr[i]),
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.C (tx_lclk_io),
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.CE (1'b1),
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.D1 (tx_data16[i+8] ^ invert_pins),
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.D2 (tx_data16[i] ^ invert_pins)
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.D2 (tx_data16[i] ^ invert_pins),
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.R (1'b0),
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.S (1'b0)
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);
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end
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endgenerate
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//FRAME
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ODDRE1
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
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oddr_frame (
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.Q (txo_frame_ddr),
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.C (tx_lclk_io),
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.CE (1'b1),
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.D1 (tx_frame16 ^ invert_pins),
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.D2 (tx_frame16 ^ invert_pins)
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.D2 (tx_frame16 ^ invert_pins),
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.R (1'b0), //reset
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.S (1'b0)
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);
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//LCLK
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ODDRE1
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
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oddr_lclk (
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.Q (txo_lclk90),
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.C (tx_lclk90),
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.CE (1'b1),
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.D1 (1'b1 ^ invert_pins),
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.D2 (1'b0 ^ invert_pins)
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.D2 (1'b0 ^ invert_pins),
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.R (1'b0),//should be no reason to reset clock, static input
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.S (1'b0)
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);
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end
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endgenerate
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//Buffer drivers
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OBUFDS obufds_data[7:0] (
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.O (txo_data_p[7:0]),
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OBUFDS obufds_data[7:0] (.O (txo_data_p[7:0]),
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.OB (txo_data_n[7:0]),
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.I (txo_data_ddr[7:0])
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);
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.I (txo_data_ddr[7:0]));
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OBUFDS obufds_frame ( .O (txo_frame_p),
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OBUFDS obufds_frame (.O (txo_frame_p),
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.OB (txo_frame_n),
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.I (txo_frame_ddr)
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);
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.I (txo_frame_ddr));
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OBUFDS obufds_lclk ( .O (txo_lclk_p),
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OBUFDS obufds_lclk (.O (txo_lclk_p),
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.OB (txo_lclk_n),
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.I (txo_lclk90)
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);
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.I (txo_lclk90));
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//Wait inputs
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generate
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if(ETYPE==1)
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