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Simplifying module
-Interrupt should be kept separate from GPIO (use PIC)
This commit is contained in:
Andreas Olofsson
parent
8cb368027c
commit
9aed3f19d2
11
gpio/README.md
Normal file
11
gpio/README.md
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GPIO
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=======
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A General Purpose IO module with all pins individually configurable as inputs or outputs. Output pins are controlled by writing to the ODATA register. Inputs are sampled by reading the IDATA register. Inputs can be configured to trigger interupts.
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121
gpio/hdl/gpio.v
121
gpio/hdl/gpio.v
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//#########################################################################
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//# GPIO (Supports up to 32 GPIO pins)
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//# GPIO
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//# -each pin can be an output or input
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//# -level and edge interrupts supported on every input pin
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//#########################################################################
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`include "gpio_regmap.v"
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module gpio(/*AUTOARG*/
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// Outputs
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reg_rdata, gpio_out, gpio_en, gpio_irq, gpio_ilat,
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reg_rdata, io_out, io_en, gpio_irq, gpio_data,
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// Inputs
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nreset, clk, reg_access, reg_packet, gpio_in
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nreset, clk, reg_access, reg_packet, io_in
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);
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//##################################################################
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@ -32,14 +31,13 @@ module gpio(/*AUTOARG*/
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output [31:0] reg_rdata; // readback data
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//IO signals
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output [N-1:0] gpio_out; // data to drive to IO pins
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output [N-1:0] gpio_en; // tristate enables for IO pins
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input [N-1:0] gpio_in; // data from IO pins
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output [N-1:0] io_out; // data to drive to IO pins
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output [N-1:0] io_en; // tristate enables for IO pins
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input [N-1:0] io_in; // data from IO pins
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//global interrupt
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output gpio_irq; // or of all interrupts
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output [31:0] gpio_ilat; // individual interrupt outputs
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output gpio_irq; // change detected on an input
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output [N-1:0] gpio_data; // individual interrupt outputs
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//##################################################################
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//# BODY
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@ -49,16 +47,9 @@ module gpio(/*AUTOARG*/
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reg [N-1:0] odata_reg;
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reg [N-1:0] oen_reg;
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reg [N-1:0] idata_reg;
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reg [N-1:0] itype_reg;
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reg [N-1:0] ipol_reg;
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reg [N-1:0] imask_reg;
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reg [N-1:0] ilat_reg;
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reg [N-1:0] gpio_reg;
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reg [AW-1:0] reg_rdata;
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//nets
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reg [N-1:0] ilat_in;
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reg [N-1:0] ilat_event;
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wire [N-1:0] gpio_sync;
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wire [N-1:0] event_posedge;
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wire [N-1:0] event_negedge;
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@ -86,7 +77,7 @@ module gpio(/*AUTOARG*/
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//################################
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//# REGISTER ACCESS DECODE
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//################################
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packet2emesh p2e(.packet_in (reg_packet[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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@ -97,26 +88,15 @@ module gpio(/*AUTOARG*/
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]));
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assign reg_write = reg_access & write_in;
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assign reg_read = reg_access & ~write_in;
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assign gpio_match = reg_access &
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(dstaddr_in[10:8]==ID);
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assign gpio_write = gpio_match & write_in;
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assign gpio_read = gpio_match & ~write_in;
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assign odata_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATA);
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assign odataand_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATAAND);
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assign odataorr_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATAORR);
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assign odataxor_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ODATAXOR);
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assign oen_write = gpio_write & (dstaddr_in[7:2]==`GPIO_OEN);
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assign idata_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IDATA);
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assign itype_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ITYPE);
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assign ipol_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IPOL);
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assign imask_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IMASK);
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assign imaskand_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IMASKAND);
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assign imaskorr_write = gpio_write & (dstaddr_in[7:2]==`GPIO_IMASKORR);
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assign ilat_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ILAT);
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assign ilatand_write = gpio_write & (dstaddr_in[7:2]==`GPIO_ILATAND);
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assign odata_write = reg_write & (dstaddr_in[7:2]==`GPIO_ODATA);
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assign odataand_write = reg_write & (dstaddr_in[7:2]==`GPIO_ODATAAND);
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assign odataorr_write = reg_write & (dstaddr_in[7:2]==`GPIO_ODATAORR);
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assign odataxor_write = reg_write & (dstaddr_in[7:2]==`GPIO_ODATAXOR);
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assign oen_write = reg_write & (dstaddr_in[7:2]==`GPIO_OEN);
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assign idata_write = reg_write & (dstaddr_in[7:2]==`GPIO_IDATA);
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//################################
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//# OUTPUT CONTROL REGISTERS
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@ -148,79 +128,14 @@ module gpio(/*AUTOARG*/
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always @ (posedge clk)
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idata_reg[N-1:0] <= gpio_sync[N-1:0];
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//ITYPE
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//0=level
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//1=edge
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always @ (posedge clk)
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if(itype_write)
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itype_reg[N-1:0] <= data_in[N-1:0];
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//IPOLARITY
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//0=positive
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//1=negative
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always @ (posedge clk)
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if(ipol_write)
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ipol_reg[N-1:0] <= data_in[N-1:0];
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//IMASK
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always @ (posedge clk)
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if(imask_write)
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imask_reg[N-1:0] <= data_in[N-1:0];
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else if(imaskand_write)
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imask_reg[N-1:0] <= imask_reg[N-1:0] & data_in[N-1:0];
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else if(imaskorr_write)
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imask_reg[N-1:0] <= imask_reg[N-1:0] | data_in[N-1:0];
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//ILAT
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always @ (posedge clk or negedge nreset)
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if(~nreset)
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ilat_reg[N-1:0] <= 'b0;
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else
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ilat_reg[N-1:0] <= ilat_in[N-1:0];
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//################################
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//# INTERRUPT CONTROL
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//################################
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//ILAT
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always @*
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for(i=0;i<N;i=i+1)
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ilat_in[i] =(ilat_write & data_in[i]) | // ilat set
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(ilat_reg[i] & ~(ilatand_write & ~data_in[i]))|// ilat clear
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(ilat_event[i]); // event
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//shadow
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always @ (posedge clk)
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gpio_reg[N-1:0] <= gpio_sync[N-1:0];
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//events
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assign event_posedge[N-1:0] = gpio_sync[N-1:0] & ~gpio_reg[N-1:0];
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assign event_negedge[N-1:0] = ~gpio_sync[N-1:0] & gpio_reg[N-1:0];
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always @*
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for(j=0;j<N;j=j+1)
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ilat_event[j] = (~itype_reg[j] & ~ipol_reg[j] & gpio_sync[j]) |
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(~itype_reg[j] & ipol_reg[j] & ~gpio_sync[j]) |
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(itype_reg[j] & ~ipol_reg[j] & event_posedge[j]) |
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(itype_reg[j] & ipol_reg[j] & event_negedge[j]);
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//global interrupt output
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assign gpio_irq = |ilat_reg[N-1:0];
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//################################
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//# READBACK
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//################################
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always @ (posedge clk)
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if(gpio_read)
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if(reg_read)
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case(dstaddr_in[7:2])
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`GPIO_OEN : reg_rdata[31:0] <= oen_reg[N-1:0];
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`GPIO_IDATA : reg_rdata[31:0] <= idata_reg[N-1:0];
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`GPIO_ITYPE : reg_rdata[31:0] <= itype_reg[N-1:0];
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`GPIO_IPOL : reg_rdata[31:0] <= ipol_reg[N-1:0];
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`GPIO_IMASK : reg_rdata[31:0] <= imask_reg[N-1:0];
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`GPIO_ILAT : reg_rdata[31:0] <= ilat_reg[N-1:0];
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default : reg_rdata[AW-1:0] <='b0;
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endcase // case (dstaddr_in[7:2])
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@ -7,13 +7,5 @@
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`define GPIO_ODATAXOR 6'h3
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`define GPIO_OEN 6'h4
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`define GPIO_IDATA 6'h5
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`define GPIO_ITYPE 6'h6
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`define GPIO_IPOL 6'h7
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`define GPIO_IMASK 6'h8
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`define GPIO_IMASKAND 6'h9
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`define GPIO_IMASKORR 6'h10
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`define GPIO_ILAT 6'h11
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`define GPIO_ILATAND 6'h12
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`endif
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