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Adding always_latch to avoid verilator warnings

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aolofsson 2021-03-02 16:49:20 -05:00
parent 1925c188c8
commit 9b63e23bda
1 changed files with 1 additions and 1 deletions
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common/hdl/oh_lat0.v
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@ -19,7 +19,7 @@ module oh_lat0 #(parameter DW = 1 // data width
.out(out[DW-1:0]));
`else
reg [DW-1:0] out_reg;
always @ (clk or in)
always_latch @ (clk or in)
if (!clk)
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];