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Implemented DMA state machine
- Work in progress
This commit is contained in:
Andreas Olofsson
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26515bc1e9
commit
9bec938914
@ -4,34 +4,185 @@
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//# Author: Andreas Olofsson #
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//# License: MIT (see below) #
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//#############################################################################
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`include "edma_regmap.vh"
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module edma_ctrl (/*AUTOARG*/
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// Outputs
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dma_state, outerloop, master_active, update,
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fetch_access, fetch_packet, dma_state, update, update2d,
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master_active,
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// Inputs
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clk, nreset, dma_en, chainmode, mastermode, access_in, wait_in
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clk, nreset, dma_en, chainmode, manualmode, mastermode, count,
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curr_descr, next_descr, reg_wait_in, access_in, wait_in
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);
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// clk, reset, config
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input clk; // main clock
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input nreset; // async active low reset
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input dma_en; // dma is enabled
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input chainmode; // chainmode configuration
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input mastermode; // dma configured in mastermode
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parameter AW = 32; // address width
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localparam PW = 2*AW+40; // fetch packet width
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parameter ID = 4'b0000; // group id for DMA regs [10:8]
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// packet control
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input access_in; // slave access
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input wait_in; // controls machine stall
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// clk, reset, config
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input clk; // main clock
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input nreset; // async active low reset
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input dma_en; // dma is enabled
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input chainmode; // chainmode configuration
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input manualmode; // descriptor fetch
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input mastermode; // dma configured in mastermode
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input [31:0] count; // current transfer count
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input [15:0] curr_descr;
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input [15:0] next_descr;
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// descriptor fetch interface
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output fetch_access; // fetch descriptor
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output [PW-1:0] fetch_packet; // fetch packet
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input reg_wait_in; // register access wait
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// slave access
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input access_in; // slave access
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input wait_in; // master/slave transfer stall
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// status
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output [2:0] dma_state; // state of dma
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output outerloop; // dma currently in outerloop (2D)
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output master_active;// master is active
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output update; // update registers
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output [3:0] dma_state; // state of dma
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output update; // update registers
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output update2d; // dma currently in outerloop (2D)
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output master_active; // master is active
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//###########################################################################
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//# BODY
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//###########################################################################
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reg [3:0] dma_state;
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wire [15:0] descr;
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wire [15:0] fetch_addr;
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wire [AW-1:0] srcaddr_out;
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wire [4:0] reg_addr;
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//###########################################
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//# STATE MACHINE
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//###########################################
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`define DMA_IDLE 4'b0000 // dma idle
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`define DMA_FETCH0 4'b0001 // fetch cfg, next-ptr, stride_in
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`define DMA_FETCH1 4'b0010 // fetch cnt_out,cnt_in, stride_out
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`define DMA_FETCH2 4'b0011 // fetch srcaddr, dstaddr
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`define DMA_FETCH3 4'b0100 // fetch srcaddr64, dstaddr64
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`define DMA_FETCH4 4'b0101 // stall (no bypass)
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`define DMA_INNER 4'b0110 // dma inner loop
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`define DMA_OUTER 4'b0111 // dma outer loop
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`define DMA_DONE 4'b1000 // dma outer loop
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`define DMA_ERROR 4'b1001 // dma error
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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dma_state[3:0] <= `DMA_IDLE;
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else if(dma_error)
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dma_state[3:0] <= `DMA_ERROR;
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else
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case(dma_state[3:0])
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`DMA_IDLE:
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casez({dma_en,manualmode})
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2'b0? : dma_state[3:0] <= `DMA_IDLE;
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2'b11 : dma_state[3:0] <= `DMA_INNER;
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2'b10 : dma_state[3:0] <= `DMA_FETCH0;
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endcase // casez (dma_reg_write_config)
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`DMA_FETCH0:
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dma_state[3:0] <= reg_wait_in ? `DMA_FETCH0 : `DMA_FETCH1;
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`DMA_FETCH1:
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dma_state[3:0] <= reg_wait_in ? `DMA_FETCH1 : `DMA_FETCH2;
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`DMA_FETCH2:
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dma_state[3:0] <= reg_wait_in ? `DMA_FETCH2 : `DMA_FETCH3;
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`DMA_FETCH3:
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dma_state[3:0] <= reg_wait_in ? `DMA_FETCH3 : `DMA_FETCH3;
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`DMA_FETCH4:
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dma_state[3:0] <= reg_wait_in ? `DMA_FETCH4 : `DMA_INNER;
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`DMA_INNER:
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casez({update,incount_zero,outcount_zero})
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3'b0?? : dma_state[3:0] <= `DMA_INNER;
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3'b10? : dma_state[3:0] <= `DMA_INNER;
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3'b110 : dma_state[3:0] <= `DMA_OUTER;
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3'b111 : dma_state[3:0] <= `DMA_DONE;
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endcase
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`DMA_OUTER:
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dma_state[3:0] <= update ? `DMA_INNER : `DMA_OUTER;
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`DMA_DONE:
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casez({chainmode,manualmode})
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2'b0? : dma_state[3:0] <= `DMA_DONE;
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2'b11 : dma_state[3:0] <= `DMA_IDLE;
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2'b10 : dma_state[3:0] <= `DMA_FETCH0;
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endcase
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`DMA_ERROR:
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dma_state[3:0] <= dma_en ? `DMA_ERROR: `DMA_IDLE;
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endcase
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//###########################################
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//# ACTIVE SIGNALS
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//###########################################
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assign dma_error = 1'b0; //TODO: define error conditions
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assign update = ~wait_in & (master_active | access_in);
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assign update2d = update & (dma_state[3:0]==`DMA_OUTER);
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assign master_active = mastermode &
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((dma_state[3:0]==`DMA_INNER) |
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(dma_state[3:0]==`DMA_OUTER));
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assign incount_zero = ~(|count[15:0]);
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assign outcount_zero = ~(|count[31:16]);
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//###########################################
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//# DESCRIPTOR FETCH ENGINE
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//###########################################
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assign fetch_access = (dma_state[3:0]==`DMA_FETCH0) |
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(dma_state[3:0]==`DMA_FETCH1) |
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(dma_state[3:0]==`DMA_FETCH2);
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// fetch address
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assign descr[15:0] = (dma_state[3:0]==`DMA_FETCH0) ? next_descr[15:0] :
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curr_descr[15:0];
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oh_mux3 #(.DW(16))
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mux3d (.out (fetch_addr[15:0]),
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.in0 (descr[15:0]), .sel0 (dma_state[3:0]==`DMA_FETCH0),
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.in1 (descr[15:0]+16'd8), .sel1 (dma_state[3:0]==`DMA_FETCH1),
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.in2 (descr[15:0]+16'd16), .sel2 (dma_state[3:0]==`DMA_FETCH2)
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);
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//address of first reg to fetch
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oh_mux3 #(.DW(5))
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mux3s (.out (reg_addr[4:0]),
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.in0 (`EDMA_CONFIG), .sel0 (dma_state[3:0]==`DMA_FETCH0),
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.in1 (`EDMA_COUNT), .sel1 (dma_state[3:0]==`DMA_FETCH1),
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.in2 (`EDMA_SRCADDR), .sel2 (dma_state[3:0]==`DMA_FETCH2)
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);
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// constructing the address to return fetch to
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assign srcaddr_out[AW-1:0] = {{(AW-11){1'b0}}, //31-11
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ID, //10-7
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reg_addr[4:0], //6-2
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2'b0}; //1-0
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// constructing fetch packet
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emesh2packet #(.AW(AW))
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e2p (//outputs
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.packet_out (fetch_packet[PW-1:0]),
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//inputs
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.write_out (1'b0),
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.datamode_out (2'b11),
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.ctrlmode_out (5'b0),
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.dstaddr_out ({{(AW-16){1'b0}},fetch_addr[15:0]}),
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.data_out ({(AW){1'b0}}),
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.srcaddr_out (srcaddr_out[AW-1:0]));
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assign update = ~wait_in &
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(master_active | access_in);
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endmodule // edma_ctrl
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../common/hdl" "../../emesh/hdl")
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// End:
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///////////////////////////////////////////////////////////////////////////////
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// The MIT License (MIT) //
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