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Removed mio autoincrement mode

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-Have this handled in a more capable DMA (no need to duplicate functionality)
-Adding frame polarity signal
This commit is contained in:
Andreas Olofsson 2016-03-23 08:29:41 -04:00
parent 01f54a859b
commit 9e00240a40
4 changed files with 15 additions and 40 deletions
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3
src/mio/hdl/mio.v
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@ -62,7 +62,6 @@ module mio (/*AUTOARG*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] addrincr; // From mio_if of mio_if.v
wire amode; // From mio_regs of mio_regs.v
wire [7:0] clkdiv; // From mio_regs of mio_regs.v
wire [15:0] clkphase0; // From mio_regs of mio_regs.v
@ -126,7 +125,6 @@ module mio (/*AUTOARG*/
.access_in (reg_access_in), // Templated
.packet_in (reg_packet_in[PW-1:0]), // Templated
.wait_in (reg_wait_in), // Templated
.addrincr (addrincr[3:0]),
.tx_full (tx_full),
.tx_prog_full (tx_prog_full),
.tx_empty (tx_empty),
@ -218,7 +216,6 @@ module mio (/*AUTOARG*/
mio_if (
/*AUTOINST*/
// Outputs
.addrincr (addrincr[3:0]),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
.wait_out (wait_out),

28
src/mio/hdl/mio_if.v
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@ -1,8 +1,8 @@
`include "mio_regmap.vh"
module mio_if (/*AUTOARG*/
// Outputs
addrincr, access_out, packet_out, wait_out, rx_wait_out,
tx_access_out, tx_packet_out,
access_out, packet_out, wait_out, rx_wait_out, tx_access_out,
tx_packet_out,
// Inputs
clk, nreset, amode, emode, lsbfirst, datasize, ctrlmode, dstaddr,
wait_in, access_in, packet_in, rx_access_in, rx_packet_in,
@ -28,7 +28,6 @@ module mio_if (/*AUTOARG*/
input [7:0] datasize; // datasize
input [4:0] ctrlmode; // emesh ctrlmode
input [AW-1:0] dstaddr; // destination address for amode
output [3:0] addrincr; // increment address for amode
// core interface
output access_out; // pass through
@ -81,7 +80,7 @@ module mio_if (/*AUTOARG*/
// adapter for PW-->MPW width (MPW>=PW)
// shift up data on msbfirst shift
assign tx_packet_out[MPW-1:0] = (~lsbfirst & emode ) ? {packet_in[PW-1:0],{(MPW-PW-8){1'b0}}} :
(~lsbfirst ) ? {packet_in[PW-1:0],{(MPW-PW){1'b0}}} :
(~lsbfirst ) ? {packet_in[PW-1:0],{(MPW-PW){1'b0}}} :
packet_in[PW-1:0];
//#################################################
@ -105,25 +104,6 @@ module mio_if (/*AUTOARG*/
(datasize[3:0]==4'd4) ? 2'b10 :
2'b11;
//#################################################
// AUTOINCREMENT LOGIC ("AMODE")
//#################################################
//creating datamode based on data size
assign addr_stride[3:0] = (datamode[1:0]==2'b00) ? 4'd1 :
(datamode[1:0]==2'b01) ? 4'd2 :
(datamode[1:0]==2'b10) ? 4'd4 :
4'd8 ;
// only update when in amode and no wait
assign addr_update = amode & ~wait_in & access_out;
// send address increment to mio_regs
assign addrincr[3:0] = addr_update ? addr_stride[3:0] :
4'b0;
//#################################################
// TRANSACTION FOR CORE (FROM RX)
//#################################################
@ -167,7 +147,7 @@ module mio_if (/*AUTOARG*/
endmodule // mio_if
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../../oh/emesh/hdl")
// verilog-library-directories:("." "../../emesh/hdl")
// End:

4
src/mio/hdl/mio_regmap.vh
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@ -7,8 +7,8 @@
`define MIO_CLKPHASE 4'd3 // clk divider config
`define MIO_ODELAY 4'd4 // output data delay element
`define MIO_IDELAY 4'd5 // input data delay element
`define MIO_ADDR0 4'd6 // destination address in amode
`define MIO_ADDR1 4'd7 // destination address in amode
`define MIO_ADDR0 4'd6 // destination address for amode
`define MIO_ADDR1 4'd7 // destination address for amode
`endif // `ifndef MIO_REGMAP_VH_

20
src/mio/hdl/mio_regs.v
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@ -5,16 +5,16 @@ module mio_regs (/*AUTOARG*/
amode, dmode, datasize, lsbfirst, ctrlmode, dstaddr, clkdiv,
clkphase0, clkphase1,
// Inputs
clk, nreset, access_in, packet_in, wait_in, addrincr, tx_full,
tx_prog_full, tx_empty, rx_full, rx_prog_full, rx_empty
clk, nreset, access_in, packet_in, wait_in, tx_full, tx_prog_full,
tx_empty, rx_full, rx_prog_full, rx_empty
);
// parameters
parameter N = 8; // number of I/O pins
parameter AW = 32; // address width
localparam PW = 2*AW+40; // packet width
parameter DEF_CFG = 0; // default enable value (1 is on)
parameter DEF_CLK = 0; // default CLKDIV value (divide by 8)
parameter DEF_CFG = 0; // reset MIO_CONFI value
parameter DEF_CLK = 0; // reset MIO_CLKDIV value
localparam DEF_RISE0 = 0; // 0 degrees
localparam DEF_FALL0 = ((DEF_CLK+8'd1)>>8'd1); // 180 degrees
localparam DEF_RISE1 = ((DEF_CLK+8'd1)>>8'd2); // 90 degrees
@ -43,7 +43,6 @@ module mio_regs (/*AUTOARG*/
output [7:0] datasize; // mio datasize
output lsbfirst; // lsb shift first
output [4:0] ctrlmode; // emode ctrlmode
input [3:0] addrincr; // address update in amode
//address
output [AW-1:0] dstaddr; // destination address for RX dmode
@ -124,13 +123,14 @@ module mio_regs (/*AUTOARG*/
assign tx_en = ~config_reg[0]; // tx disable
assign rx_en = ~config_reg[1]; // rx disable
assign emode = config_reg[3:2]==2'b00; // emesh packets
assign dmode = config_reg[3:2]==2'b01; // pure data mode (streaming)
assign dmode = config_reg[3:2]==2'b01; // data mode (streaming)
assign amode = config_reg[3:2]==2'b10; // auto address mode
assign datasize[7:0] = config_reg[11:4]; // number of flits per packet
assign ddr_mode = config_reg[12]; // dual data rate mode
assign lsbfirst = config_reg[13]; // lsb-first transmit
assign ctrlmode[4:0] = config_reg[18:14]; // amode ctrlmode
assign framepol = config_reg[14]; // frame polarity
assign ctrlmode[4:0] = config_reg[20:16]; // ctrlmode
//###############################
//# STATUS
//################################
@ -188,12 +188,10 @@ module mio_regs (/*AUTOARG*/
addr_reg[31:0] <= data_in[31:0];
else if(addr1_write)
addr_reg[63:32] <= data_in[31:0];
else
addr_reg[63:0] <= addr_reg[63:0] + addrincr[3:0];
assign dstaddr[AW-1:0] = addr_reg[AW-1:0];
endmodule // io_cfg
// Local Variables:
// verilog-library-directories:("." "../../../oh/emesh/hdl" "../../../oh/common/hdl")
// verilog-library-directories:("." "../../emesh/hdl" "../../../oh/common/hdl")
// End: