From a0625a7d0f06a42bedfcd361baa8180ba18ea6e3 Mon Sep 17 00:00:00 2001
From: aolofsson <andreas@zeroasic.com>
Date: Mon, 26 Apr 2021 10:26:24 -0400
Subject: [PATCH] Adding WIP/broken warning

---
 README.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/README.md b/README.md
index 06d18e7..593bbc9 100644
--- a/README.md
+++ b/README.md
@@ -3,6 +3,12 @@
 
 ## Introduction
 
+!!! WARNING!!!
+* Main branch is Work In Progress (ie broken)
+* For a stable version, seee Tag V1.0
+
+------
+
 OH! is an open-source library of hardware building blocks based on silicon proven design practices at 0.35um to 28nm. The library is being used by Adapteva in designing its next generation ASIC.
 
 The library is written in standard Verilog (2005) and contains over 25,000 lines of Verilog code, over 150 separate modules. Examples of functionality include: FIFOs, SPI (master/slave), GPIO, high speed links, memories, clock circuits, synchronization primitives,interrupt controller, DMA.