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Increasing timeout value on simctrl to reasonable default

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aolofsson 2022-06-17 14:39:23 -04:00
parent f6610a0f80
commit a31e16fb25
1 changed files with 26 additions and 31 deletions
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57
src/stdlib/dv/oh_simctrl.v
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@ -1,7 +1,7 @@
/* verilator lint_off STMTDLY */
module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
parameter CFG_CLK2_PERIOD = 20,
parameter CFG_TIMEOUT = 500
parameter CFG_TIMEOUT = 5000
)
(
//control signals to drive
@ -13,25 +13,25 @@ module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
output vss, // driving vss
//input from testbench
input dut_active, // dut reset sequence is done
input stim_done, // stimulus is done
input stim_done, // stimulus is done
input test_done, // test is done
input test_diff // diff between dut and reference
);
localparam CFG_CLK1_PHASE = CFG_CLK1_PERIOD/2;
localparam CFG_CLK2_PHASE = CFG_CLK2_PERIOD/2;
//signal declarations
reg vdd;
reg vss;
reg vss;
reg nreset;
reg start;
reg clk1=0;
reg clk2=0;
reg [6:0] clk1_phase;
reg [6:0] clk2_phase;
reg test_fail;
reg test_fail;
integer seed,r;
reg [1023:0] testname;
@ -43,15 +43,15 @@ module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
r=$value$plusargs("TESTNAME=%s", testname[1023:0]);
$timeformat(-9, 0, " ns", 20);
end
`ifndef VERILATOR
`ifndef VERILATOR
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, testbench);
end
`endif
//#################################
// RANDOM NUMBER GENERATOR
// (SEED SUPPLIED EXERNALLY)
@ -59,22 +59,22 @@ module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
initial
begin
r=$value$plusargs("SEED=%s", seed);
//$display("SEED=%d", seed);
//$display("SEED=%d", seed);
`ifdef CFG_RANDOM
clk1_phase = 1 + {$random(seed)}; //generate random values
clk2_phase = 1 + {$random(seed)}; //generate random values
`else
clk1_phase = CFG_CLK1_PHASE;
clk2_phase = CFG_CLK2_PHASE;
clk1_phase = CFG_CLK1_PHASE;
clk2_phase = CFG_CLK2_PHASE;
`endif
//$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);
//$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);
end
//#################################
//CLK GENERATORS
//#################################
always
always
#(clk1_phase) clk1 = ~clk1;
always
@ -85,11 +85,11 @@ module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
//#################################
initial
begin
begin
#(1)
nreset = 'b0;
vdd = 'b0;
vss = 'b0;
vss = 'b0;
#(clk1_phase * 10 + 10) //ramping voltage
vdd = 'bx;
#(clk1_phase * 10 + 10) //voltage is safe
@ -110,9 +110,9 @@ module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
begin
$display("-------------------");
$display("TEST %0s STARTED", testname);
start <= 1'b1;
start <= 1'b1;
end
//STOP SIMULATION ON END
always @ (posedge clk1 or negedge nreset)
if(!nreset)
@ -124,25 +124,20 @@ module oh_simctrl #( parameter CFG_CLK1_PERIOD = 10,
if(test_fail | test_diff)
$display("TEST %0s FAILED", testname);
else
$display("TEST %0s PASSED", testname);
$display("TEST %0s PASSED", testname);
$finish;
end
else if (test_diff)
test_fail <= 1'b1;
//#################################
// TIMEOUT
//#################################
initial
begin
#(CFG_TIMEOUT)
$display("TEST %0s FAILED ON TIMEOUT",testname);
#(CFG_TIMEOUT)
$display("TEST %0s FAILED ON TIMEOUT",testname);
$finish;
end
endmodule // oh_simctrl