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Fixing pushback bug

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* Fixed pushback bug at fifo (DUH!)
* Need to verify random pushback at all tx/rx ports
This commit is contained in:
Andreas Olofsson 2015-11-02 16:16:10 -05:00
parent ff3af0b21c
commit a3b0d9b75c
2 changed files with 39 additions and 39 deletions
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48
memory/hdl/fifo_async.v
View File

@ -1,4 +1,3 @@
//`include "../../elink/hdl/elink_constants.v"
module fifo_async
(/*AUTOARG*/
// Outputs
@ -7,9 +6,9 @@ module fifo_async
wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104; //FIFO width
parameter DEPTH = 32; //FIFO depth
parameter DW = 104; //FIFO width
parameter DEPTH = 32; //FIFO depth
//##########
//# RESET/CLOCK
//##########
@ -35,24 +34,26 @@ module fifo_async
output valid;
`ifdef TARGET_CLEAN
fifo_async_model fifo_model (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
`ifdef TARGET_SIMPLE
fifo_async_model
#(.DEPTH(DEPTH),
.DW(DW))
fifo_model (.full (),
.prog_full (prog_full),
.almost_full (full),
/*AUTOINST*/
// Outputs
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
`elsif TARGET_XILINX
generate
@ -77,8 +78,7 @@ module fifo_async
end
endgenerate

30
memory/hdl/fifo_cdc.v
View File

@ -41,9 +41,9 @@ module fifo_cdc (/*AUTOARG*/
wire valid;
reg access_out;
assign wr_en = access_in;//&~full
assign wr_en = access_in & ~full;
assign rd_en = ~empty & ~wait_in;
assign wait_out = full;
assign wait_out = full;
//Keep access high until "acknowledge"
always @ (posedge clk_out or posedge reset_out)
@ -58,19 +58,19 @@ module fifo_cdc (/*AUTOARG*/
fifo_async fifo (.prog_full (full),//stay safe for now
.full (),
// Outputs
.dout (packet_out[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (reset_in),
.rd_rst (reset_out),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en)
);
// Outputs
.dout (packet_out[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (reset_in),
.rd_rst (reset_out),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en)
);
endmodule // fifo_cdc