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-Renaming constants files as ".vh"
-Cleanup parameters
This commit is contained in:
Andreas Olofsson 2016-02-26 19:08:40 -05:00
parent 9aed3f19d2
commit a5194a30a3
25 changed files with 249 additions and 171 deletions
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2
accelerator/hdl/accelerator.v
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@ -1,4 +1,4 @@
`include "accelerator_regmap.v"
`include "accelerator_regmap.vh"
module accelerator (/*AUTOARG*/
// Outputs
m_wr_access, m_wr_packet, m_rd_access, m_rd_packet, m_rr_wait,

0
accelerator/hdl/accelerator_regmap.v → accelerator/hdl/accelerator_regmap.vh
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1
accelerator/hdl/axi_accelerator.v
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@ -1,7 +1,6 @@
//########################################################
// ACCELERATOR + AXI_SLAVE + AXI_MASTER
//########################################################
`include "accelerator_regmap.v"
module axi_accelerator(/*AUTOARG*/
// Outputs
irq, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,

8
common/dv/dv_ctrl.v
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@ -39,8 +39,8 @@ module dv_ctrl(/*AUTOARG*/
r=$value$plusargs("SEED=%s", seed);
$display("SEED=%d", seed);
`ifdef CFG_RANDOM
clk1_phase = {$random(seed)}; //generate random values
clk2_phase = {$random(seed)}; //generate random values
clk1_phase = 1 + {$random(seed)}; //generate random values
clk2_phase = 1 + {$random(seed)}; //generate random values
`else
clk1_phase = CFG_CLK1_PHASE;
clk2_phase = CFG_CLK2_PHASE;
@ -52,13 +52,13 @@ module dv_ctrl(/*AUTOARG*/
//CLK1 GENERATOR
//#################################
always
#(clk1_phase + 1) clk1 = ~clk1; //add one to avoid "DC" state
#(clk1_phase) clk1 = ~clk1; //add one to avoid "DC" state
//#################################
//CLK2 GENERATOR
//#################################
always
#(clk2_phase + 1) clk2 = ~clk2;
#(clk2_phase) clk2 = ~clk2;
//#################################
//RESET

2
elink/dv/tests/test_burst.emf
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@ -1,4 +1,4 @@
00000000_00000000_810F021c_05_0010 //zere out monitor
00000000_00000400_810F0210_05_0010 // enable burst
810d0000_abcd0000_80800000_07_0000 // write double
810d0008_55550008_80800008_07_0000 // write double
810d0010_abcd0010_80800010_07_0000 // write double

2
elink/hdl/axi_elink.v
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@ -1,7 +1,7 @@
//########################################################
// ELINK + AXI_SLAVE + AXI_MASTER
//########################################################
`include "elink_regmap.v"
`include "elink_regmap.vh"
module axi_elink(/*AUTOARG*/
// Outputs
elink_active, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,

2
elink/hdl/ecfg_if.v
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@ -1,4 +1,4 @@
`include "elink_regmap.v"
`include "elink_regmap.vh"
module ecfg_if (/*AUTOARG*/
// Outputs
mi_mmu_en, mi_dma_en, mi_cfg_en, mi_we, mi_addr, mi_din,

9
elink/hdl/elink_cfg.v
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@ -1,11 +1,4 @@
/*
########################################################################
MASTER ENABLE, CLOCKS, CHIP-ID
########################################################################
*/
`include "elink_regmap.v"
`include "elink_regmap.vh"
module elink_cfg (/*AUTOARG*/
// Outputs
txwr_gated_access, etx_soft_reset, erx_soft_reset, clk_config,

9
elink/hdl/elink_constants.v
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@ -1,9 +0,0 @@
`ifndef ELINK_CONSTANTS_V_
`define ELINK_CONSTANTS_V_
//target platform (mutually exclusive)
`define TARGET_XILINX //xilinx specific blocks
//`define TARGET_ALTERA //altera specifics
//`define TARGET_ASIC //asic specific blocks
`endif

0
elink/hdl/elink_regmap.v → elink/hdl/elink_regmap.vh
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2
elink/hdl/erx_arbiter.v
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@ -1,4 +1,4 @@
`include "elink_regmap.v"
`include "elink_regmap.vh"
module erx_arbiter (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,

2
elink/hdl/erx_cfg.v
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@ -1,4 +1,4 @@
`include "elink_regmap.v"
`include "elink_regmap.vh"
module erx_cfg (/*AUTOARG*/
// Outputs
mmu_access, dma_access, mailbox_access, ecfg_access, ecfg_packet,

191
elink/hdl/erx_clocks.v
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@ -1,22 +1,24 @@
`include "elink_constants.v"
`include "elink_constants.vh"
module erx_clocks (/*AUTOARG*/
// Outputs
rx_lclk, rx_lclk_div4, rx_active, erx_nreset, erx_io_nreset,
// Inputs
sys_nreset, soft_reset, tx_active, sys_clk, rx_clkin
);
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Frequency Settings (Mhz)
//Frequency Settings (Mhz)
parameter FREQ_RXCLK = 300;
parameter FREQ_IDELAY = 200;
parameter RXCLK_PHASE = 0; //270; //-90 deg rxclk phase shift
parameter PLL_VCO_MULT = 4; //RX
parameter RXCLK_PHASE = 0; // 270;
parameter PLL_VCO_MULT = 4; // RX
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
//Override reset counter size for simulation
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Don't touch these! (derived parameters)
localparam real RXCLK_PERIOD = 1000.000000 / FREQ_RXCLK; //? Why is the period needed here?
@ -131,90 +133,91 @@ module erx_clocks (/*AUTOARG*/
.clk (rx_lclk_div4),
.nrst_in (rx_nreset)
);
`ifdef TARGET_XILINX
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(IREF_DIVIDE), // idelay ref clk
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),//RXCLK_PHASE
.CLKOUT5_PHASE(0.0),//RXCLK_PHASE/4
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(idelay_ref_clk_pll),
.CLKOUT4(rx_lclk_pll),
.CLKOUT5(rx_lclk_div4_pll),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(rx_lclk_fb),
.CLKFBOUT(rx_lclk_fb),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),//??
.DO(), //??
.LOCKED(pll_locked)
);
//Clock network
BUFG i_lclk_bufg (.I(rx_lclk_pll), .O(rx_lclk)); //300Mhz
BUFG i_lclk_div4_bufg (.I(rx_lclk_div4_pll), .O(rx_lclk_div4)); //(300Mhz/4)
BUFG i_idelay_bufg (.I(idelay_ref_clk_pll),.O(idelay_ref_clk));//idelay ctrl clock
//two clock synchronizer for lock signal
oh_dsync dsync (.dout (pll_locked_sync),
.clk (sys_clk),
.din (pll_locked)
);
//###########################
// Idelay controller
//###########################
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset));
`endif // `ifdef TARGET_XILINX
generate
if(TARGET=="XILINX")
begin
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(IREF_DIVIDE), // idelay ref clk
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),//RXCLK_PHASE
.CLKOUT5_PHASE(0.0),//RXCLK_PHASE/4
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(idelay_ref_clk_pll),
.CLKOUT4(rx_lclk_pll),
.CLKOUT5(rx_lclk_div4_pll),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(rx_lclk_fb),
.CLKFBOUT(rx_lclk_fb),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),//??
.DO(), //??
.LOCKED(pll_locked)
);
//Clock network
BUFG i_lclk_bufg (.I(rx_lclk_pll), .O(rx_lclk)); //300Mhz
BUFG i_lclk_div4_bufg (.I(rx_lclk_div4_pll), .O(rx_lclk_div4)); //(300Mhz/4)
BUFG i_idelay_bufg (.I(idelay_ref_clk_pll),.O(idelay_ref_clk));//idelay ctrl clock
//two clock synchronizer for lock signal
oh_dsync dsync (.dout (pll_locked_sync),
.clk (sys_clk),
.din (pll_locked)
);
//###########################
// Idelay controller
//###########################
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset));
end // if (TARGET=="XILINX")
endgenerate
endmodule // eclocks
// Local Variables:

9
elink/hdl/erx_protocol.v
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@ -1,9 +1,6 @@
/*
This block handles the autoincrement needed for bursting and detects
read responses
*/
`include "elink_regmap.v"
//############################################################
//#This block handles the autoincrement needed for bursting
//############################################################
module erx_protocol (/*AUTOARG*/
// Outputs
erx_access, erx_packet,

12
elink/hdl/etx_cfg.v
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@ -1,9 +1,7 @@
/*
########################################################################
ELINK TX CONFIGURATION REGISTER FILE
########################################################################
*/
`include "elink_regmap.v"
//########################################################################
//# ELINK TX CONFIGURATION REGISTER FILE
//########################################################################
`include "elink_regmap.vh"
module etx_cfg (/*AUTOARG*/
// Outputs
cfg_mmu_access, etx_cfg_access, etx_cfg_packet, tx_enable,
@ -17,6 +15,8 @@ module etx_cfg (/*AUTOARG*/
//##################################################################
//# INTERFACE
//##################################################################
//parameters
parameter AW = 32;
parameter PW = 2*AW+40;
parameter RFAW = 6;

46
elink/hdl/etx_clocks.v
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@ -1,4 +1,4 @@
`include "elink_constants.v"
`include "elink_constants.vh"
module etx_clocks (/*AUTOARG*/
// Outputs
tx_lclk_io, tx_lclk90, tx_lclk_div4, cclk_p, cclk_n, etx_nreset,
@ -7,18 +7,23 @@ module etx_clocks (/*AUTOARG*/
sys_nreset, soft_reset, sys_clk
);
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_TXCLK = 300;
parameter FREQ_CCLK = 600;
parameter TXCLK_PHASE = 90; //txclk phase shift
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
//Override reset counter size for simulation
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Don't touch these! (derived parameters)
parameter MMCM_VCO_MULT = 12; //TX + CCLK
localparam real SYSCLK_PERIOD = 1000.000000 / FREQ_SYSCLK;
@ -163,9 +168,12 @@ module etx_clocks (/*AUTOARG*/
// Inputs
.clk (tx_lclk_div4),
.nrst_in (tx_nreset));
`ifdef TARGET_XILINX
generate
if(TARGET=="XILINX")
begin
//###########################
// MMCM FOR TXCLK + CCLK
//###########################
@ -266,14 +274,22 @@ module etx_clocks (/*AUTOARG*/
.OB (cclk_n),
.I (cclk_oddr)
);
`else // !`ifdef TARGET_XILINX
assign cclk_p = sys_clk;
assign cclk_n = sys_clk;
assign tx_lclk_io = sys_clk;
assign tx_lclk_div4 = sys_clk;
assign tx_lclk90 = sys_clk;
`endif // `ifdef TARGET_XILINX
end // if (TARGET=="XILINX")
else
begin
assign cclk_p = sys_clk;
assign cclk_n = sys_clk;
assign tx_lclk_io = sys_clk;
assign tx_lclk_div4 = sys_clk;
assign tx_lclk90 = sys_clk;
end
endgenerate
endmodule // eclocks
// Local Variables:

18
elink/hdl/etx_protocol.v
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@ -1,14 +1,10 @@
/*
*
* This module converts the packet interface to a 64bit wide format
* suitable for sending out to a parallel to serial shift register.
* The frame signal is sent along together with the data making.
* The goal is to minimize the amount of logic done on the high speed
* domain.
*
*
*/
`include "elink_regmap.v"
//#####################################################################
//# This module converts the packet interface to a 64bit wide format
//# suitable for sending out to a parallel to serial shift register.
//# The frame signal is sent along together with the data making.
//# The goal is to minimize the amount of logic done on the high speed
//# domain.
//#####################################################################
module etx_protocol (/*AUTOARG*/
// Outputs
etx_rd_wait, etx_wr_wait, etx_wait, tx_burst, tx_access,

2
etrace/hdl/etrace.v
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@ -1,4 +1,4 @@
`include "etrace_regmap.v"
`include "etrace_regmap.vh"
module etrace (/*AUTOARG*/
// Outputs
data_access_out, data_packet_out, cfg_access_out, cfg_packet_out,

3
etrace/hdl/etrace_regmap.v
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@ -1,3 +0,0 @@
`define ETRACE_CFG 6'd0 //configuration
`define ETRACE_REGS 4'hF //group decode
`define ETRACE_MEM 4'hA //group decode

3
etrace/hdl/etrace_regmap.vh Normal file
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@ -0,0 +1,3 @@
`define ETRACE_CFG 6'd0 //configuration
`define ETRACE_REGS 4'hF //group decode
`define ETRACE_MEM 4'hA //group decode

BIN
parallella/fpga/headless/parallella.bit.bin
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Binary file not shown.

1
parallella/fpga/parallella_io.xdc
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@ -55,6 +55,7 @@ set_property PACKAGE_PIN H17 [get_ports cclk_n]
# Epiphany TX
#####################
set_property IOSTANDARD LVDS_25 [get_ports {txo*}]
set_property IOSTANDARD LVDS_25 [get_ports {txi*}]
set_property PACKAGE_PIN F17 [get_ports txo_lclk_n]
set_property PACKAGE_PIN A20 [get_ports {txo_data_n[0]}]
set_property PACKAGE_PIN B20 [get_ports {txo_data_n[1]}]

2
pic/hdl/pic.v
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@ -1,4 +1,4 @@
`include "pic_regmap.v"
`include "pic_regmap.vh"
//###########################################################################
//# IRQC: Simple nessted interrupt controller
//#

0
pic/hdl/pic_regmap.v → pic/hdl/pic_regmap.vh
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94
spi/hdl/spi_regs.v
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@ -30,24 +30,106 @@ module spi_regs (/*AUTOARG*/
//io interface
output [7:0] txdata; // data in txfifo
input [7:0] rxdata; // data for rxfifo
//##################################################################
//# BODY
//##################################################################
reg [31:0] status_reg;
reg [31:0] config_reg;
reg [31:0] cfg_reg;
reg [31:0] ilat_reg;
reg [31:0] imask_reg;
reg [31:0] delay_reg;
reg [31:0] tx_reg;
reg [31:0] rx_reg;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
endmodule // spi_regs
//################################
//# REGISTER ACCESS DECODE
//################################
packet2emesh p2e(.packet_in (reg_packet[PW-1:0]),
/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]));
assign reg_write = reg_access & write_in;
assign reg_read = reg_access & ~write_in;
assign cfg_write = reg_write & (dstaddr_in[7:2]==`SPI_CFG);
assign status_write = reg_write & (dstaddr_in[7:2]==`SPI_STATUS);
assign ilat_write = reg_write & (dstaddr_in[7:2]==`SPI_ILAT);
assign imask_write = reg_write & (dstaddr_in[7:2]==`SPI_IMASK);
assign delay_write = reg_write & (dstaddr_in[7:2]==`SPI_DELAY);
assign tx_write = reg_write & (dstaddr_in[7:2]==`SPI_TX);
////////////////////////
//CFG
always @ (posedge clk)
if(cfg_write)
cfg_reg[31:0] <= data_in[31:0];
assign spi_en = cfg_reg[1];
assign cpol = cfg_reg[2];
assign cpha = cfg_reg[3];
assign master_mode = cfg_reg[4];
assign manual_mode = cfg_reg[5]; //
assign irqen = cfg_reg[6]; //enable spi interrupt
assign clkdiv[3:0] = cfg_reg[11:8];
////////////////////////
//STATUS
always @ (posedge clk)
if(status_write)
status_reg[31:0] <= data_in[31:0];
else
status_reg[31:0] <= status_in[31:0];
////////////////////////
//ILAT
always @ (posedge clk)
if(status_write)
status_reg[31:0] <= data_in[31:0];
else
status_reg[31:0] <= status_in[31:0];
////////////////////////
//IMASK
always @ (posedge clk)
if(status_write)
//################################
//# READBACK
//################################
always @ (posedge clk)
if(reg_read)
case(dstaddr_in[7:2])
`SPI_CFG : reg_rdata[31:0] <= cfg_reg[31:0];
`SPI_STATUS : reg_rdata[31:0] <= status_reg[31:0];
`SPI_ILAT : reg_rdata[31:0] <= ilat_reg[31:0];
`SPI_IMASK : reg_rdata[31:0] <= imask_reg[31:0];
`SPI_DELAY : reg_rdata[31:0] <= delay_reg[31:0];
`SPI_RX : reg_rdata[31:0] <= rx_reg[31:0];
endcase // case (dstaddr_in[7:2])
endmodule // spi_regs
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End: