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Changing SPI command structure

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- Read/write commands should be at MSBs (7:6)
- Fixed fifo read race..need to look at this again
This commit is contained in:
Andreas Olofsson 2016-03-10 17:33:52 -05:00
parent 3ca89dca2b
commit a7003be8e9
2 changed files with 2 additions and 3 deletions
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2
spi/hdl/spi_master_io.v
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@ -117,7 +117,7 @@ module spi_master_io(/*AUTOARG*/
assign byte_done = (bit_count[2:0]==3'b000);
//read fifo on phase match (due to one cycle pipeline latency
assign fifo_read = ((spi_state[1:0]==`SPI_IDLE) & phase_match ) |
assign fifo_read = ((spi_state[1:0]==`SPI_SETUP) & phase_match) |
((spi_state[1:0]==`SPI_DATA) & phase_match & byte_done);
//load once per byte

3
spi/hdl/spi_slave_io.v
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@ -147,8 +147,7 @@ module spi_slave_io(/*AUTOARG*/
(command_reg[7:6]==2'b00) &
(spi_state[1:0]==`SPI_DATA);
assign spi_read =
command_reg[7:6]==2'b11; //read from sclk reg
assign spi_read = command_reg[7:6]==2'b11; //read from sclk reg
assign spi_remote = command_reg[7:6]==2'b10; //send remote request