diff --git a/spi/hdl/spi_master_io.v b/spi/hdl/spi_master_io.v
index 85682ae..74d829f 100644
--- a/spi/hdl/spi_master_io.v
+++ b/spi/hdl/spi_master_io.v
@@ -117,7 +117,7 @@ module spi_master_io(/*AUTOARG*/
    assign byte_done  = (bit_count[2:0]==3'b000);
 
    //read fifo on phase match (due to one cycle pipeline latency
-   assign fifo_read = ((spi_state[1:0]==`SPI_IDLE) & phase_match ) |
+   assign fifo_read = ((spi_state[1:0]==`SPI_SETUP) & phase_match) |
 		      ((spi_state[1:0]==`SPI_DATA) & phase_match & byte_done);
 
    //load once per byte
diff --git a/spi/hdl/spi_slave_io.v b/spi/hdl/spi_slave_io.v
index f1a2f40..7baf483 100644
--- a/spi/hdl/spi_slave_io.v
+++ b/spi/hdl/spi_slave_io.v
@@ -147,8 +147,7 @@ module spi_slave_io(/*AUTOARG*/
 			  (command_reg[7:6]==2'b00) &
 			  (spi_state[1:0]==`SPI_DATA);
   
-   assign spi_read      = 
-			  command_reg[7:6]==2'b11; //read from sclk reg  
+   assign spi_read      = command_reg[7:6]==2'b11; //read from sclk reg  
 
    assign spi_remote    = command_reg[7:6]==2'b10; //send remote request