From a94911808a38e563cd5512f7d8d059150cba17c9 Mon Sep 17 00:00:00 2001 From: aolofsson Date: Mon, 27 Jun 2022 00:23:48 -0400 Subject: [PATCH] Changing testbench to be a stub --- stdlib/testbench/testbench.v | 170 ++++++----------------------------- 1 file changed, 25 insertions(+), 145 deletions(-) diff --git a/stdlib/testbench/testbench.v b/stdlib/testbench/testbench.v index e9798be..343ee58 100644 --- a/stdlib/testbench/testbench.v +++ b/stdlib/testbench/testbench.v @@ -1,161 +1,41 @@ //############################################################################# -//# Function: Common testbench for simulator and fpga # +//# Function: Stub testbench # //############################################################################# //# Author: Andreas Olofsson # //# License: MIT (see LICENSE file in OH! repository) # //############################################################################# - +`timescale 1ns / 1ns module testbench - #(parameter PW = 256, // packet width - parameter CW = 16, // control width + #(parameter PW = 256, // packet total width + parameter CW = 16, // packet control width parameter N = 32, // ctrl/status width - parameter PERIOD_CLK = 10, // core clock period - parameter PERIOD_FASTCLK = 20, // fast clock period - parameter PERIOD_SLOWCLK = 20, // slow clock period - parameter TIMEOUT = 5000, // timeout value - parameter RANDOMIZE = 0, // 1=randomize period - parameter SIMULATE = 1, // 1=VERILOG SIM - parameter FILENAME = "NONE", // Simulus hexfile for $readmemh parameter DEPTH = 8192, // simulus memory depth - parameter SEED = 32'haaaaaaaa,// seed for random generation parameter TARGET = "DEFAULT" // physical synthesis/sim target ) ( // control signals to drive - input nreset, // async active low reset - input clk, // core clock - input fastclk, - input slowclk, - input go, // start signal - input [N-1:0] ctrl, //generic ctrl vector - output [N-1:0] status, //generic status vector - output dut_error, - output dut_done, + input nreset, // async active low reset + input clk, // core clock + input fastclk, // fast clock + input slowclk, //slow clock + input [2:0] mode, //0=idle,1=load,2=go,3=rng,4=bypass + input [N-1:0] ctrl, // generic ctrl vector + input [PW-1:0] seed, // seed(s) for rng // external write interface - input ext_clk, - input [PW-1:0] ext_packet, - input ext_ready, - input ext_valid + input ext_clk, //ext packet clock + input ext_valid, // ext valid signal + input [PW-1:0] ext_packet, // ext packet + input ext_ready, // external ready to receive + // dut response packets + output dut_clk, // due packet clock + output dut_valid, //dut packet valid signal + output [PW-1:0] dut_packet, // dut packet to drive + output dut_ready, // dut is ready for packet + // dut status interface + output [N-1:0] dut_status, // generic status vector + output dut_error,// dut error flag (leads to failure) + output dut_done, // test done + output dut_fail // test failed ); - //################################# - // LOCAL WIRES, PARAMETERS - //################################# - - wire [PW-1:0] tb_packet; - wire tb_ready; - wire tb_valid; - wire [N-1:0] tb_ctrl; - wire tb_nreset; - wire tb_clk; - wire tb_slowclk; - wire tb_fastclk; - wire tb_go; - - /*AUTOINPUT*/ - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire dut_active; // From tb_dut of tb_dut.v - wire [PW-1:0] dut_packet; // From tb_dut of tb_dut.v - wire dut_ready; // From tb_dut of tb_dut.v - wire [N-1:0] dut_status; // From tb_dut of tb_dut.v - wire dut_valid; // From tb_dut of tb_dut.v - // End of automatics - - //################################# - // CONTROL INTERFACE - //################################# - - assign tb_ctrl[N-1:0] = ctrl[N-1:0]; - - generate - if (SIMULATE) begin - /*oh_simctrl AUTO_TEMPLATE ( - .dut_\(.*\) (dut_\1[]), - .\(.*\) (tb_\1[]), - ); - */ - oh_simctrl #(.PERIOD_CLK(PERIOD_CLK), - .PERIOD_SLOWCLK(PERIOD_SLOWCLK), - .PERIOD_FASTCLK(PERIOD_FASTCLK), - .TIMEOUT(TIMEOUT), - .RANDOMIZE(RANDOMIZE)) - oh_simctrl(/*AUTOINST*/ - // Outputs - .nreset (tb_nreset), // Templated - .clk (tb_clk), // Templated - .fastclk (tb_fastclk), // Templated - .slowclk (tb_slowclk), // Templated - .go (tb_go), // Templated - // Inputs - .dut_active (dut_active), // Templated - .dut_done (dut_done), // Templated - .dut_error (dut_error)); // Templated - end - else begin - assign tb_nreset = nreset; - assign tb_clk = clk; - assign tb_slowclk = slowclk; - assign tb_fastclk = fastclk; - assign tb_go = go; - end - endgenerate - - //################################# - // DUT - //################################# - /*tb_dut AUTO_TEMPLATE ( - .dut_\(.*\) (dut_\1[]), - .\(.*\) (tb_\1[]), - ); - */ - tb_dut #(.PW(PW), - .N(N), - .SEED(SEED), - .TARGET(TARGET)) - tb_dut(.valid (tb_valid), - .packet (tb_packet[PW-1:0]), - .ready (tb_ready), - /*AUTOINST*/ - // Outputs - .dut_active (dut_active), // Templated - .dut_error (dut_error), // Templated - .dut_done (dut_done), // Templated - .dut_status (dut_status[N-1:0]), // Templated - .dut_valid (dut_valid), // Templated - .dut_packet (dut_packet[PW-1:0]), // Templated - .dut_ready (dut_ready), // Templated - // Inputs - .clk (tb_clk), // Templated - .fastclk (tb_fastclk), // Templated - .slowclk (tb_slowclk), // Templated - .nreset (tb_nreset), // Templated - .go (tb_go), // Templated - .ctrl (tb_ctrl[N-1:0])); // Templated - - //################################# - // STIMULUS - //################################# - - oh_stimulus #(.PW(PW), - .CW(CW), - .DEPTH(DEPTH), - .TARGET(TARGET), - .FILENAME(FILENAME)) - oh_stimulus(.dut_clk (clk), - .stim_valid (tb_valid), - .stim_packet (tb_packet[PW-CW-1:0]), - .stim_done (tb_done), - /*AUTOINST*/ - // Inputs - .nreset (nreset), - .go (go), - .ext_clk (ext_clk), - .ext_valid (ext_valid), - .ext_packet (ext_packet[PW-1:0]), - .dut_ready (dut_ready)); - endmodule // testbench -// Local Variables: -// verilog-library-directories:("." "../rtl") -// End: