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Fixing typos

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This commit is contained in:
Andreas Olofsson 2015-11-06 22:40:59 -05:00
parent b6c95e5b94
commit aa940c2a39
3 changed files with 52 additions and 33 deletions
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48
parallella/fpga/parallella_7020_io.xdc
View File

@ -11,27 +11,27 @@
##################################
# IOs to be used with zc7020 ONLY
##################################
set_property PACKAGE_PIN Y12 [get_ports {GPIO_P[12]}]
set_property PACKAGE_PIN Y13 [get_ports {GPIO_N[12]}]
set_property PACKAGE_PIN W11 [get_ports {GPIO_P[13]}]
set_property PACKAGE_PIN Y11 [get_ports {GPIO_N[13]}]
set_property PACKAGE_PIN V11 [get_ports {GPIO_P[14]}]
set_property PACKAGE_PIN V10 [get_ports {GPIO_N[14]}]
set_property PACKAGE_PIN T9 [get_ports {GPIO_P[15]}]
set_property PACKAGE_PIN U10 [get_ports {GPIO_N[15]}]
set_property PACKAGE_PIN W10 [get_ports {GPIO_P[16]}]
set_property PACKAGE_PIN W9 [get_ports {GPIO_N[16]}]
set_property PACKAGE_PIN U9 [get_ports {GPIO_P[17]}]
set_property PACKAGE_PIN U8 [get_ports {GPIO_N[17]}]
set_property PACKAGE_PIN V8 [get_ports {GPIO_P[18]}]
set_property PACKAGE_PIN W8 [get_ports {GPIO_N[18]}]
set_property PACKAGE_PIN Y9 [get_ports {GPIO_P[19]}]
set_property PACKAGE_PIN Y8 [get_ports {GPIO_N[19]}]
set_property PACKAGE_PIN Y7 [get_ports {GPIO_P[20]}]
set_property PACKAGE_PIN Y6 [get_ports {GPIO_N[20]}]
set_property PACKAGE_PIN U7 [get_ports {GPIO_P[21]}]
set_property PACKAGE_PIN V7 [get_ports {GPIO_N[21]}]
set_property PACKAGE_PIN V6 [get_ports {GPIO_P[22]}]
set_property PACKAGE_PIN W6 [get_ports {GPIO_N[22]}]
set_property PACKAGE_PIN T5 [get_ports {GPIO_P[23]}]
set_property PACKAGE_PIN U5 [get_ports {GPIO_N[23]}]
set_property PACKAGE_PIN Y12 [get_ports {gpio_p[12]}]
set_property PACKAGE_PIN Y13 [get_ports {gpio_n[12]}]
set_property PACKAGE_PIN W11 [get_ports {gpio_p[13]}]
set_property PACKAGE_PIN Y11 [get_ports {gpio_n[13]}]
set_property PACKAGE_PIN V11 [get_ports {gpio_p[14]}]
set_property PACKAGE_PIN V10 [get_ports {gpio_n[14]}]
set_property PACKAGE_PIN T9 [get_ports {gpio_p[15]}]
set_property PACKAGE_PIN U10 [get_ports {gpio_n[15]}]
set_property PACKAGE_PIN W10 [get_ports {gpio_p[16]}]
set_property PACKAGE_PIN W9 [get_ports {gpio_n[16]}]
set_property PACKAGE_PIN U9 [get_ports {gpio_p[17]}]
set_property PACKAGE_PIN U8 [get_ports {gpio_n[17]}]
set_property PACKAGE_PIN V8 [get_ports {gpio_p[18]}]
set_property PACKAGE_PIN W8 [get_ports {gpio_n[18]}]
set_property PACKAGE_PIN Y9 [get_ports {gpio_p[19]}]
set_property PACKAGE_PIN Y8 [get_ports {gpio_n[19]}]
set_property PACKAGE_PIN Y7 [get_ports {gpio_p[20]}]
set_property PACKAGE_PIN Y6 [get_ports {gpio_n[20]}]
set_property PACKAGE_PIN U7 [get_ports {gpio_p[21]}]
set_property PACKAGE_PIN V7 [get_ports {gpio_n[21]}]
set_property PACKAGE_PIN V6 [get_ports {gpio_p[22]}]
set_property PACKAGE_PIN W6 [get_ports {gpio_n[22]}]
set_property PACKAGE_PIN T5 [get_ports {gpio_p[23]}]
set_property PACKAGE_PIN U5 [get_ports {gpio_n[23]}]

34
parallella/fpga/parallella_io.xdc
View File

@ -35,20 +35,27 @@ set_property PACKAGE_PIN P20 [get_ports hdmi_int]
#####################
# I2C
#####################
set_property IOSTANDARD LVCMOS25 [get_ports {i2c_*}]
set_property PACKAGE_PIN N18 [get_ports i2c_scl]
set_property IOSTANDARD LVCMOS25 [get_ports i2c_scl]
set_property PACKAGE_PIN N17 [get_ports i2c_sda]
set_property IOSTANDARD LVCMOS25 [get_ports i2c_sda]
#####################
# Epiphany Interface
# Epiphany Reset
#####################
set_property PACKAGE_PIN G14 [get_ports {chip_nreset}]
set_property IOSTANDARD LVCMOS25 [get_ports {chip_nreset}]
set_property DRIVE 4 [get_ports {chip_nreset}]
set_property PACKAGE_PIN G14 [get_ports {chip_nreset}]
#####################
# Epiphany Clock
#####################
set_property IOSTANDARD LVDS_25 [get_ports {cclk*}]
set_property PACKAGE_PIN H17 [get_ports cclk_n]
set_property PACKAGE_PIN F17 [get_ports tx_lclk_n]
#####################
# Epiphany TX
#####################
set_property IOSTANDARD LVDS_25 [get_ports {txo*}]
set_property PACKAGE_PIN F17 [get_ports txo_lclk_n]
set_property PACKAGE_PIN A20 [get_ports {txo_data_n[0]}]
set_property PACKAGE_PIN B20 [get_ports {txo_data_n[1]}]
set_property PACKAGE_PIN D20 [get_ports {txo_data_n[2]}]
@ -58,10 +65,20 @@ set_property PACKAGE_PIN F20 [get_ports {txo_data_n[5]}]
set_property PACKAGE_PIN G18 [get_ports {txo_data_n[6]}]
set_property PACKAGE_PIN G20 [get_ports {txo_data_n[7]}]
set_property PACKAGE_PIN G15 [get_ports txo_frame_n]
set_property PACKAGE_PIN H18 [get_ports txi_wr_wait_n]
#####################
# Wait signals
#####################
set_property IOSTANDARD LVCMOS25 [get_ports {txi_rd_wait_*}]
set_property PACKAGE_PIN J15 [get_ports txi_rd_wait_p]
set_property PACKAGE_PIN H18 [get_ports tx_wr_wait_n]
set_property PACKAGE_PIN K18 [get_ports rx_lclk_n]
#####################
# Epiphany RX
#####################
set_property IOSTANDARD LVDS_25 [get_ports {rx*}]
set_property PACKAGE_PIN K18 [get_ports rxi_lclk_n]
set_property PACKAGE_PIN J19 [get_ports {rxi_data_n[0]}]
set_property PACKAGE_PIN L15 [get_ports {rxi_data_n[1]}]
set_property PACKAGE_PIN L17 [get_ports {rxi_data_n[2]}]
@ -78,6 +95,7 @@ set_property PACKAGE_PIN J16 [get_ports rxo_wr_wait_n]
# GPIO
# First 12 pairs are present on all parts, next 12 on 7020 only
#######################
set_property IOSTANDARD LVCMOS25 [get_ports {gpio*}]
set_property PACKAGE_PIN T16 [get_ports {gpio_p[0]}]
set_property PACKAGE_PIN U17 [get_ports {gpio_n[0]}]
set_property PACKAGE_PIN V16 [get_ports {gpio_p[1]}]

3
parallella/fpga/parallella_timing.xdc
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@ -1,3 +1,4 @@
create_clock -period 3.333 -name RX_lclk_p -waveform {0.000 1.666} [get_ports RX_lclk_p]
create_clock -period 3.333 -name rxi_lclk_p -waveform {0.000 1.666} [get_ports rxi_lclk_p]