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Fixing connection errors for AW=64 in SPI

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This commit is contained in:
Andreas Olofsson 2016-03-28 16:45:10 -04:00
parent 813dd3c17e
commit ab19abd965
4 changed files with 48 additions and 33 deletions
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4
src/spi/dv/dut_spi.v
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@ -69,9 +69,7 @@ module dut(/*AUTOARG*/
//drive through master, observe on slave
spi #(.AW(AW),
.UREGS(UREGS)
)
.UREGS(UREGS))
master (.m_miso (s_miso),
.master_mode (1'b1),
.s_miso (),

21
src/spi/hdl/spi_master_fifo.v
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@ -55,16 +55,17 @@ module spi_master_fifo (/*AUTOARG*/
//# DECODE
//###################################
packet2emesh p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
packet2emesh #(.AW(AW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
assign datasize[7:0] = emode ? (PW/SW-1'b1) :

23
src/spi/hdl/spi_master_regs.v
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@ -61,7 +61,7 @@ module spi_master_regs (/*AUTOARG*/
reg [7:0] clkdiv_reg;
reg [7:0] cmd_reg;
reg [63:0] rx_reg;
reg [31:0] reg_rdata;
reg [AW-1:0] reg_rdata;
reg autotran;
reg access_out;
reg [AW-1:0] dstaddr_out;
@ -211,16 +211,17 @@ module spi_master_regs (/*AUTOARG*/
assign wait_out = fifo_wait;
emesh2packet e2p (.write_out (1'b1),
.srcaddr_out (32'b0),
.data_out (reg_rdata[31:0]),
/*AUTOINST*/
// Outputs
.packet_out (packet_out[PW-1:0]),
// Inputs
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]));
emesh2packet #(.AW(AW))
e2p (.write_out (1'b1),
.srcaddr_out ({(AW){1'b0}}),
.data_out (reg_rdata[AW-1:0]),
/*AUTOINST*/
// Outputs
.packet_out (packet_out[PW-1:0]),
// Inputs
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]));
endmodule // spi_master_regs

33
src/spi/hdl/spi_slave_regs.v
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@ -59,6 +59,16 @@ module spi_slave_regs (/*AUTOARG*/
wire [63:0] core_data;
integer i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From pe2 of packet2emesh.v
wire [AW-1:0] data_in; // From pe2 of packet2emesh.v
wire [1:0] datamode_in; // From pe2 of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From pe2 of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From pe2 of packet2emesh.v
wire write_in; // From pe2 of packet2emesh.v
// End of automatics
//#####################################
//# SPI DECODE
//#####################################
@ -70,18 +80,23 @@ module spi_slave_regs (/*AUTOARG*/
//#####################################
//# CORE DECODE
//#####################################
assign wait_out = 1'b0;
packet2emesh #(.AW(AW))
pe2 (.write_in (),
.datamode_in (),
.ctrlmode_in (),
.dstaddr_in (),
.srcaddr_in (core_data[63:32]),
.data_in (core_data[31:0]),
packet2emesh #(.AW(AW))
pe2 (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
.packet_in (packet_in[PW-1:0]));
assign core_data[63:0]={srcaddr_in[31:0],data_in[31:0]};
//#####################################
//# CONFIG [0]
//#####################################