Implemented frame polarity in mio

-Seems like the place to do this, more advanced framing should be done outside of mio

src/mio/hdl/mio.v

@@ -71,6 +71,7 @@ module mio (/*AUTOARG*/
    wire			ddr_mode;		// From mio_regs of mio_regs.v
    wire [AW-1:0]	dstaddr;		// From mio_regs of mio_regs.v
    wire			emode;			// From mio_regs of mio_regs.v
+   wire			framepol;		// From mio_regs of mio_regs.v
    wire			io_clk;			// From oh_clockdiv of oh_clockdiv.v
    wire			lsbfirst;		// From mio_regs of mio_regs.v
    wire			rx_access_io2c;		// From mio_dp of mio_dp.v
@@ -114,6 +115,7 @@ module mio (/*AUTOARG*/
 	     .amode			(amode),
 	     .datasize			(datasize[7:0]),
 	     .lsbfirst			(lsbfirst),
+	     .framepol			(framepol),
 	     .ctrlmode			(ctrlmode[4:0]),
 	     .dstaddr			(dstaddr[AW-1:0]),
 	     .clkdiv			(clkdiv[7:0]),
@@ -193,6 +195,7 @@ module mio (/*AUTOARG*/
 	  .datasize			(datasize[7:0]),
 	  .ddr_mode			(ddr_mode),
 	  .lsbfirst			(lsbfirst),
+	  .framepol			(framepol),
 	  .tx_en			(tx_en),
 	  .rx_en			(rx_en),
 	  .tx_wait			(tx_wait),

src/mio/hdl/mio_dp.v

@@ -3,8 +3,8 @@ module mio_dp (/*AUTOARG*/
    tx_full, tx_prog_full, tx_empty, rx_full, rx_prog_full, rx_empty,
    tx_access, tx_packet, rx_wait, wait_out, access_out, packet_out,
    // Inputs
-   clk, io_clk, nreset, datasize, ddr_mode, lsbfirst, tx_en, rx_en,
-   tx_wait, rx_clk, rx_access, rx_packet, access_in, packet_in,
+   clk, io_clk, nreset, datasize, ddr_mode, lsbfirst, framepol, tx_en,
+   rx_en, tx_wait, rx_clk, rx_access, rx_packet, access_in, packet_in,
    wait_in
    );
 
@@ -24,6 +24,7 @@ module mio_dp (/*AUTOARG*/
    input [7:0] 	   datasize;     // size of data transmitted
    input 	   ddr_mode;	 // dual data rate mode
    input 	   lsbfirst;     // send data lsbfirst
+   input 	   framepol;     // polarity of frame signal   
    input 	   tx_en;        // enable transmit
    input 	   rx_en;        // enable receive
    
@@ -97,6 +98,7 @@ module mio_dp (/*AUTOARG*/
 	.datasize			(datasize[7:0]),
 	.ddr_mode			(ddr_mode),
 	.lsbfirst			(lsbfirst),
+	.framepol			(framepol),
 	.rx_clk				(rx_clk),
 	.rx_access			(rx_access),
 	.rx_packet			(rx_packet[N-1:0]),

src/mio/hdl/mio_regs.v

@@ -2,8 +2,8 @@
 module mio_regs (/*AUTOARG*/
    // Outputs
    wait_out, access_out, packet_out, tx_en, rx_en, ddr_mode, emode,
-   amode, dmode, datasize, lsbfirst, ctrlmode, dstaddr, clkdiv,
-   clkphase0, clkphase1,
+   amode, dmode, datasize, lsbfirst, framepol, ctrlmode, dstaddr,
+   clkdiv, clkphase0, clkphase1,
    // Inputs
    clk, nreset, access_in, packet_in, wait_in, tx_full, tx_prog_full,
    tx_empty, rx_full, rx_prog_full, rx_empty
@@ -42,6 +42,7 @@ module mio_regs (/*AUTOARG*/
    output 	   dmode;        // mio packet mode
    output [7:0]    datasize;     // mio datasize   
    output 	   lsbfirst;     // lsb shift first
+   output 	   framepol;     // framepolarity (0=actrive high)   
    output [4:0]    ctrlmode;     // emode ctrlmode
    
    //address

src/mio/hdl/mrx.v

@@ -3,8 +3,8 @@ module mrx (/*AUTOARG*/
    // Outputs
    rx_empty, rx_full, rx_prog_full, rx_wait, access_out, packet_out,
    // Inputs
-   clk, nreset, datasize, ddr_mode, lsbfirst, rx_clk, rx_access,
-   rx_packet, wait_in
+   clk, nreset, datasize, ddr_mode, lsbfirst, framepol, rx_clk,
+   rx_access, rx_packet, wait_in
    );
 
    //#####################################################################
@@ -23,7 +23,8 @@ module mrx (/*AUTOARG*/
    input [7:0] 	   datasize;    // size of data transmitted (in bytes, 0=1 byte)
    input 	   ddr_mode;
    input 	   lsbfirst;
-
+   input 	   framepol;
+   
    //status
    output 	   rx_empty;	// rx fifo is empty
    output 	   rx_full;	// rx fifo is full (should never happen!) 
@@ -131,6 +132,7 @@ module mrx (/*AUTOARG*/
 	   .rx_clk			(rx_clk),
 	   .ddr_mode			(ddr_mode),
 	   .lsbfirst			(lsbfirst),
+	   .framepol			(framepol),
 	   .rx_packet			(rx_packet[N-1:0]),
 	   .rx_access			(rx_access));
   

src/mio/hdl/mrx_io.v

@@ -5,7 +5,7 @@ module mrx_io (/*AUTOARG*/
    // Outputs
    io_access, io_packet,
    // Inputs
-   nreset, rx_clk, ddr_mode, lsbfirst, rx_packet, rx_access
+   nreset, rx_clk, ddr_mode, lsbfirst, framepol, rx_packet, rx_access
    );
 
    //#####################################################################
@@ -20,6 +20,7 @@ module mrx_io (/*AUTOARG*/
    input 	    rx_clk;        // clock for IO
    input 	    ddr_mode;      // select between sdr/ddr data
    input 	    lsbfirst;      // shufle data in msbfirst mode
+   input 	    framepol;      // frame polarity
    
    //IO interface
    input [N-1:0]    rx_packet;     // data for IO
@@ -45,15 +46,21 @@ module mrx_io (/*AUTOARG*/
 		     .nrst_in	(nreset)
 		     );
       
+   //########################################
+   //# SELECT FRAME POLARITY
+   //########################################
+
+   assign rx_frame =  framepol ^ rx_access;
+   
    //########################################
    //# ACCESS (SDR)
    //########################################
 
    always @ (posedge rx_clk or negedge io_nreset)
      if(!nreset)
-       io_access   <= 1'b0;
+       io_access <= 1'b0;
      else
-       io_access   <= rx_access;
+       io_access <= rx_frame;
    
    //########################################
    //# DATA (DDR) 
@@ -63,7 +70,7 @@ module mrx_io (/*AUTOARG*/
    data_iddr(.q1			(ddr_data[N-1:0]),
 	     .q2			(ddr_data[2*N-1:N]),
 	     .clk			(rx_clk),
-	     .ce			(rx_access),
+	     .ce			(rx_frame),
 	     .din			(rx_packet[N-1:0])
 	     );
    //########################################
@@ -72,10 +79,10 @@ module mrx_io (/*AUTOARG*/
    //select 2nd byte (stall on this signal)
 
    always @ (posedge rx_clk)
-     if(~rx_access)
+     if(~rx_frame)
        byte0_sel <= 1'b1;
      else if (~ddr_mode)
-       byte0_sel <= rx_access ^ byte0_sel;
+       byte0_sel <= rx_frame ^ byte0_sel;
    
    always @ (posedge rx_clk)
      if(byte0_sel)