From ae6cdc912ef00efe3d8e84b95bf72ea656509875 Mon Sep 17 00:00:00 2001 From: "Andreas.Olofsson" Date: Mon, 20 Jul 2020 14:50:09 -0400 Subject: [PATCH] Mapping cs42 to csa32 -Better synthesis results --- common/hdl/oh_csa42.v | 59 ++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/common/hdl/oh_csa42.v b/common/hdl/oh_csa42.v index 0bfb28d..3de7ffe 100644 --- a/common/hdl/oh_csa42.v +++ b/common/hdl/oh_csa42.v @@ -11,44 +11,39 @@ module oh_csa42 #( parameter DW = 1 // data width input [DW-1:0] in1,//input input [DW-1:0] in2,//input input [DW-1:0] in3,//input - input [DW-1:0] cin,//carry in + input cin,//intra stage carry in + output cout, //intra stage carry out (=2x weight of s/c) output [DW-1:0] s, //sum - output [DW-1:0] c, //carry - output [DW-1:0] cout //carry out + output [DW-1:0] c //carry ); -`ifdef CFG_ASIC - asic_csa42 i_csa42[DW-1:0] (.s(s[DW-1:0]), - .cout(cout[DW-1:0]), - .c(c[DW-1:0]), - .cin(cin[DW-1:0]), - .in3(in3[DW-1:0]), - .in2(in2[DW-1:0]), - .in1(in1[DW-1:0]), - .in0(in0[DW-1:0])); -`else - wire [DW-1:0] s_int; + wire [DW-1:0] sum_int; + wire [DW:0] carry_int; - assign s[DW-1:0] = in0[DW-1:0] ^ - in1[DW-1:0] ^ - in2[DW-1:0] ^ - in3[DW-1:0] ^ - cin[DW-1:0]; - - assign s_int[DW-1:0] = in1[DW-1:0] ^ - in2[DW-1:0] ^ - in3[DW-1:0]; - - assign c[DW-1:0] = (in0[DW-1:0] & s_int[DW-1:0]) | - (in0[DW-1:0] & cin[DW-1:0]) | - (s_int[DW-1:0] & cin[DW-1:0]); - - assign cout[DW-1:0] = (in1[DW-1:0] & in2[DW-1:0]) | - (in1[DW-1:0] & in3[DW-1:0]) | - (in2[DW-1:0] & in3[DW-1:0]); -`endif + //Edges + assign carry_int[0] = cin; + assign cout = carry_int[DW]; + //Full Adders + oh_csa32 #(.DW(DW)) + fa0 (//inputs + .in0(in0[DW-1:0]), + .in1(in1[DW-1:0]), + .in2(in2[DW-1:0]), + //outputs + .c(c[DW-1:0]), + .s(sum_int[DW-1:0])); + oh_csa32 #(.DW(DW)) + fa1 (//inputs + .in0(in3[DW-1:0]), + .in1(sum_int[DW-1:0]), + .in2(carry_int[DW-1:0]), + //outputs + .c(carry_int[DW:1]), + .s(s[DW-1:0])); + endmodule // oh_csa42 +