From afd6e868408264e9d42fe01726d041778b7083d2 Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Sat, 25 Apr 2015 23:28:52 -0400 Subject: [PATCH] Fixing etx pipeline -Fixed one bug inserted during edits, causing double transactions -Added pipeline stall logic to all units --- elink/hdl/etx.v | 5 ++++- elink/hdl/etx_arbiter.v | 12 ++++++------ elink/hdl/etx_protocol.v | 40 ++++++++++++++++++++++------------------ 3 files changed, 32 insertions(+), 25 deletions(-) diff --git a/elink/hdl/etx.v b/elink/hdl/etx.v index 83beae9..b37effa 100644 --- a/elink/hdl/etx.v +++ b/elink/hdl/etx.v @@ -74,6 +74,7 @@ module etx(/*AUTOARG*/ wire emmu_access; // From emmu of emmu.v wire [PW-1:0] emmu_packet; // From emmu of emmu.v wire etx_access; // From etx_arbiter of etx_arbiter.v + wire etx_io_wait; // From etx_protocol of etx_protocol.v wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v wire etx_rd_wait; // From etx_protocol of etx_protocol.v wire etx_remap_access; // From etx_remap of etx_remap.v @@ -241,7 +242,7 @@ module etx(/*AUTOARG*/ .txrr_fifo_packet (txrr_fifo_packet[PW-1:0]), .etx_rd_wait (etx_rd_wait), .etx_wr_wait (etx_wr_wait), - .etx_wait (etx_wait)); + .etx_io_wait (etx_io_wait)); /************************************************************/ /* REMAPPING (SHIFT) DESTINATION ADDRESS */ @@ -318,6 +319,7 @@ module etx(/*AUTOARG*/ .etx_wr_wait (etx_wr_wait), .etx_\(.*\) (emmu_\1[]), .etx_wait (etx_wait), + .etx_io_wait (etx_io_wait), ); */ etx_protocol etx_protocol (/*AUTOINST*/ @@ -325,6 +327,7 @@ module etx(/*AUTOARG*/ .etx_rd_wait (etx_rd_wait), // Templated .etx_wr_wait (etx_wr_wait), // Templated .etx_wait (etx_wait), // Templated + .etx_io_wait (etx_io_wait), // Templated .tx_frame_par (tx_frame_par[7:0]), .tx_data_par (tx_data_par[63:0]), // Inputs diff --git a/elink/hdl/etx_arbiter.v b/elink/hdl/etx_arbiter.v index ff31598..1bfa626 100644 --- a/elink/hdl/etx_arbiter.v +++ b/elink/hdl/etx_arbiter.v @@ -22,7 +22,7 @@ module etx_arbiter (/*AUTOARG*/ tx_lclk_div4, reset, ecfg_tx_ctrlmode_bp, ecfg_tx_ctrlmode, txwr_fifo_empty, txwr_fifo_packet, txrd_fifo_empty, txrd_fifo_packet, txrr_fifo_empty, txrr_fifo_packet, etx_rd_wait, - etx_wr_wait, etx_wait + etx_wr_wait, etx_io_wait ); parameter PW = 104; @@ -57,7 +57,7 @@ module etx_arbiter (/*AUTOARG*/ output etx_rr; input etx_rd_wait; input etx_wr_wait; - input etx_wait; + input etx_io_wait; //regs @@ -86,9 +86,9 @@ module etx_arbiter (/*AUTOARG*/ // FIFO read enables (one hot) // Hold until transaction has been accepted by IO - assign txrr_fifo_read = rr_ready & (~etx_access | etx_wait); - assign txrd_fifo_read = rd_ready & (~etx_access | etx_wait); - assign txwr_fifo_read = wr_ready & (~etx_access | etx_wait); + assign txrr_fifo_read = rr_ready & (~etx_access | etx_io_wait); + assign txrd_fifo_read = rd_ready & (~etx_access | etx_io_wait); + assign txwr_fifo_read = wr_ready & (~etx_access | etx_io_wait); //Selecting control mode on slave transcations assign txrd_ctrlmode[3:0] = ecfg_tx_ctrlmode_bp ? ecfg_tx_ctrlmode[3:0] : @@ -116,7 +116,7 @@ module etx_arbiter (/*AUTOARG*/ txwr_ctrlmode[3:0], txwr_fifo_packet[3:0]}; end - else if (etx_wait) + else if (~etx_io_wait) begin etx_access <= 1'b0; end diff --git a/elink/hdl/etx_protocol.v b/elink/hdl/etx_protocol.v index 91b3ab9..68de060 100644 --- a/elink/hdl/etx_protocol.v +++ b/elink/hdl/etx_protocol.v @@ -10,7 +10,8 @@ module etx_protocol (/*AUTOARG*/ // Outputs - etx_rd_wait, etx_wr_wait, etx_wait, tx_frame_par, tx_data_par, + etx_rd_wait, etx_wr_wait, etx_wait, etx_io_wait, tx_frame_par, + tx_data_par, // Inputs etx_access, etx_packet, ecfg_tx_tp_enable, ecfg_dataout, ecfg_tx_enable, ecfg_tx_gpio_enable, reset, tx_lclk_div4, @@ -26,7 +27,8 @@ module etx_protocol (/*AUTOARG*/ input [PW-1:0] etx_packet; output etx_rd_wait; output etx_wr_wait; - output etx_wait; + output etx_wait; //for pipeline + output etx_io_wait; //for arbiter //Enables transmit test pattern input ecfg_tx_tp_enable; @@ -45,7 +47,7 @@ module etx_protocol (/*AUTOARG*/ //############ //# Local regs & wires //############ - reg etx_cycle; //Cycle 0 or 1 + reg etx_sample; //hold for second cycle reg [7:0] tx_frame_par; reg [127:0] tx_data_reg; //sample transaction on one clock cycle reg rd_wait_sync; @@ -80,15 +82,15 @@ module etx_protocol (/*AUTOARG*/ begin if(reset) begin - etx_cycle <= 1'b0; + etx_sample <= 1'b1; tx_frame_par[7:0] <= 8'd0; tx_data_reg[127:0] <= 'd0; end else begin - if( etx_access & ~etx_cycle ) //first cycle (0) + if( etx_access & etx_sample ) //first cycle begin - etx_cycle <= 1'b1; + etx_sample <= 1'b0; tx_frame_par[7:0] <= 8'h3F; tx_data_reg[127:0] <= {etx_data[31:0], etx_srcaddr[31:0], @@ -100,24 +102,24 @@ module etx_protocol (/*AUTOARG*/ etx_dstaddr[3:0], etx_datamode[1:0], etx_write, etx_access // B5 }; end - else if( etx_cycle ) //second cycle (1) + else if(~etx_sample ) //second cycle (1) begin - etx_cycle <= 1'b0; + etx_sample <= 1'b1; tx_frame_par[7:0] <= 8'hFF; end else begin - etx_cycle <= 1'b0; - tx_frame_par[7:0] <= 8'h00; - tx_data_reg[127:0] <= 64'd0; + etx_sample <= 1'b1; + tx_frame_par[7:0] <= 'd0; + tx_data_reg[127:0] <= 'd0; end end // else: !if(reset) end // always @ ( posedge txlclk_p or posedge reset ) - //First/second cycle select - assign tx_data_par[63:0] = etx_cycle ? tx_data_reg[127:64]: - tx_data_reg[63:0]; + //After first sample, etx_sample-->0 use as indicator to sample in data. + assign tx_data_par[63:0] = ~etx_sample ? tx_data_reg[63:0] : //first cycle + tx_data_reg[127:64];//all others, 0 or upper //############################# //# Wait signals (async) @@ -135,10 +137,12 @@ module etx_protocol (/*AUTOARG*/ //# Pipeline stall //############################# - assign etx_wait = etx_cycle | - etx_rd_wait | - etx_wr_wait; - + assign etx_io_wait = ~etx_sample; + + assign etx_wait = etx_io_wait | + etx_rd_wait | + etx_wr_wait; + endmodule // etx_protocol // Local Variables: