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Fixing clock divider

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- asic needs a fixed cell for generated clock constraints
- fixing glitching on selectors, sampling with latch before mux (stable high)
This commit is contained in:
Andreas Olofsson 2016-07-09 17:03:07 -04:00
parent 6b050220d8
commit b1871f1867
1 changed files with 26 additions and 12 deletions
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38
src/common/hdl/oh_clockdiv.v
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@ -32,8 +32,9 @@ module oh_clockdiv
reg clkout1_reg; reg clkout1_reg;
reg clkout1_shift; reg clkout1_shift;
reg [2:0] period; reg [2:0] period;
wire wire period_match;
period_match; wire [3:0] clk1_sel;
wire [1:0] clk0_sel;
//########################################### //###########################################
//# CHANGE DETECT (count 8 periods) //# CHANGE DETECT (count 8 periods)
@ -84,15 +85,21 @@ period_match;
clkout0_reg <= 1'b1; clkout0_reg <= 1'b1;
else if(clkfall0) else if(clkfall0)
clkout0_reg <= 1'b0; clkout0_reg <= 1'b0;
// clock mux
assign clk0_sel[1] = (clkdiv[7:0]==8'd0); // not implemented
assign clk0_sel[0] = ~(clkdiv[7:0]==8'd0);
//bypass divider on "divide by 1" oh_clockmux #(.N(2))
//TODO: Fix clock glitch! iclkmux0 (.clkout(clkout0),
assign clkout0 = (clkdiv[7:0]==8'd0) ? clk : // bypass .clk(clk),
clkout0_reg; // all others .en(clk0_sel[1:0]),
.clkin({clk, clkout0_reg}));
//########################################### //###########################################
//# CLKOUT1 //# CLKOUT1
//########################################### //###########################################
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
if(!nreset) if(!nreset)
clkout1_reg <= 1'b0; clkout1_reg <= 1'b0;
@ -104,12 +111,19 @@ period_match;
// creating divide by 2 shifted clock with negedge // creating divide by 2 shifted clock with negedge
always @ (negedge clk) always @ (negedge clk)
clkout1_shift <= clkout1_reg; clkout1_shift <= clkout1_reg;
//TODO: Fix clock glitch! // clock mux
assign clkout1 = (clkdiv[7:0]==8'd0) ? clk : //bypass assign clk1_sel[3] = 1'b0; // not implemented
(clkdiv[7:0]==8'd1) ? clkout1_shift : //div2 assign clk1_sel[2] = (clkdiv[7:0]==8'd0); // div1 (bypass)
clkout1_reg; //all others assign clk1_sel[1] = (clkdiv[7:0]==8'd1); // div2 clock
assign clk1_sel[0] = |clkdiv[7:1]; // all others
oh_clockmux #(.N(4))
iclkmux1 (.clkout(clkout1),
.clk(clk),
.en( clk1_sel[3:0]),
.clkin({1'b0, clk, clkout1_shift, clkout1_reg}));
endmodule // oh_clockdiv endmodule // oh_clockdiv