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Xilinx models
-adding ODDR model -configuring the ecfg (rx/tx/clk) in testbench
This commit is contained in:
Andreas Olofsson
parent
bdec6c1067
commit
b1a9f502ca
@ -1,129 +1,134 @@
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module dv_elink_tb();
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/* verilator lint_off STMTDLY */
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//REGS
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reg clk;
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reg reset;
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reg go;
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reg [1:0] datamode;
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reg ext_access;
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reg ext_write;
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reg [1:0] ext_datamode;
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reg [3:0] ext_ctrlmode;
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reg [31:0] ext_dstaddr;
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reg [31:0] ext_data;
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reg [31:0] ext_srcaddr;
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reg ext_wr_wait;
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reg ext_rd_wait;
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reg init;
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//Forever clock
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always
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#10 clk = ~clk;
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//Reset
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initial
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begin
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#0
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reset = 1'b1; // reset is active
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go = 1'b0;
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clk = 1'b0;
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datamode = 2'b11;
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#400
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//Setting config clocks to higher value to speed sims
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dv_elink.elink.ecfg.ecfg_clk_reg[15:0]=16'h0066;
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reset = 1'b0; // at time 100 release reset
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#1000
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go = 1'b1;
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#2000
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datamode = 2'b10;
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#3000
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datamode = 2'b01;
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#4000
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datamode = 2'b00;
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#10000
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$finish;
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end
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//Notes:The testbench connects a 64 bit master to a 32 bit slave
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//To make this work, we limit the addresses to 64 bit aligned
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always @ (posedge clk)
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if(reset)
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begin
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ext_access <=1'b0; //empty
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ext_write <=1'b1;
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ext_datamode[1:0] <=2'b0;
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ext_ctrlmode[3:0] <=4'b0;
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ext_data[31:0] <=32'b0;
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ext_dstaddr[31:0] <=32'b0;
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ext_srcaddr[31:0] <=32'b0;
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ext_rd_wait <=1'b0;
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ext_wr_wait <=1'b0;
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end
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else if ((go & ~ext_access) | (ext_access & ~dut_wr_wait))
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begin
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ext_access <= 1'b1;
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ext_data[31:0] <= ext_data[31:0] + 32'b1;
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ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode)
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ext_srcaddr[31:0] <= ext_srcaddr[31:0] + 32'd8;//(32'b1<<datamode)
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ext_datamode[1:0] <= datamode[1:0];
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end
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//Waveform dump
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`ifndef TARGET_VERILATOR
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0, dv_elink_tb);
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end
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`endif
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire dut_access; // From dv_elink of dv_elink.v
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wire [3:0] dut_ctrlmode; // From dv_elink of dv_elink.v
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wire [31:0] dut_data; // From dv_elink of dv_elink.v
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wire [1:0] dut_datamode; // From dv_elink of dv_elink.v
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wire [31:0] dut_dstaddr; // From dv_elink of dv_elink.v
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wire dut_failed; // From dv_elink of dv_elink.v
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wire dut_passed; // From dv_elink of dv_elink.v
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wire dut_rd_wait; // From dv_elink of dv_elink.v
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wire [31:0] dut_srcaddr; // From dv_elink of dv_elink.v
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wire dut_wr_wait; // From dv_elink of dv_elink.v
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wire dut_write; // From dv_elink of dv_elink.v
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// End of automatics
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//dut
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dv_elink dv_elink(/*AUTOINST*/
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// Outputs
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.dut_passed (dut_passed),
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.dut_failed (dut_failed),
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.dut_wr_wait (dut_wr_wait),
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.dut_rd_wait (dut_rd_wait),
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.dut_access (dut_access),
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.dut_write (dut_write),
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.dut_datamode (dut_datamode[1:0]),
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.dut_ctrlmode (dut_ctrlmode[3:0]),
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.dut_dstaddr (dut_dstaddr[31:0]),
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.dut_srcaddr (dut_srcaddr[31:0]),
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.dut_data (dut_data[31:0]),
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// Inputs
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.clk (clk),
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.reset (reset),
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.ext_access (ext_access),
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.ext_write (ext_write),
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.ext_datamode (ext_datamode[1:0]),
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.ext_ctrlmode (ext_ctrlmode[3:0]),
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.ext_dstaddr (ext_dstaddr[31:0]),
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.ext_data (ext_data[31:0]),
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.ext_srcaddr (ext_srcaddr[31:0]),
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.ext_wr_wait (ext_wr_wait),
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.ext_rd_wait (ext_rd_wait));
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endmodule // dv_elink_tb
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module dv_elink_tb();
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/* verilator lint_off STMTDLY */
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//REGS
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reg clk;
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reg reset;
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reg go;
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reg [1:0] datamode;
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reg ext_access;
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reg ext_write;
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reg [1:0] ext_datamode;
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reg [3:0] ext_ctrlmode;
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reg [31:0] ext_dstaddr;
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reg [31:0] ext_data;
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reg [31:0] ext_srcaddr;
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reg ext_wr_wait;
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reg ext_rd_wait;
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reg init;
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//Forever clock
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always
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#10 clk = ~clk;
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//Reset
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initial
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begin
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#0
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reset = 1'b1; // reset is active
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go = 1'b0;
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clk = 1'b0;
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datamode = 2'b11;
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#400
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//clock config
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dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0066;
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//tx config
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dv_elink.elink.ecfg.ecfg_tx_reg[8:0] = 9'h001;
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//rx config
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dv_elink.elink.ecfg.ecfg_tx_reg[4:0] = 5'h01;
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reset = 1'b0; // at time 100 release reset
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#1000
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go = 1'b1;
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#2000
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datamode = 2'b10;
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#3000
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datamode = 2'b01;
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#4000
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datamode = 2'b00;
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#10000
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$finish;
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end
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//Notes:The testbench connects a 64 bit master to a 32 bit slave
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//To make this work, we limit the addresses to 64 bit aligned
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always @ (posedge clk)
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if(reset)
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begin
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ext_access <=1'b0; //empty
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ext_write <=1'b1;
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ext_datamode[1:0] <=2'b0;
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ext_ctrlmode[3:0] <=4'b0;
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ext_data[31:0] <=32'b0;
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ext_dstaddr[31:0] <=32'b0;
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ext_srcaddr[31:0] <=32'b0;
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ext_rd_wait <=1'b0;
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ext_wr_wait <=1'b0;
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end
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else if ((go & ~ext_access) | (ext_access & ~dut_wr_wait))
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begin
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ext_access <= 1'b1;
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ext_data[31:0] <= ext_data[31:0] + 32'b1;
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ext_dstaddr[31:0] <= ext_dstaddr[31:0] + 32'd8;//(32'b1<<datamode)
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ext_srcaddr[31:0] <= ext_srcaddr[31:0] + 32'd8;//(32'b1<<datamode)
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ext_datamode[1:0] <= datamode[1:0];
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end
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//Waveform dump
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`ifndef TARGET_VERILATOR
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0, dv_elink_tb);
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end
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`endif
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire dut_access; // From dv_elink of dv_elink.v
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wire [3:0] dut_ctrlmode; // From dv_elink of dv_elink.v
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wire [31:0] dut_data; // From dv_elink of dv_elink.v
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wire [1:0] dut_datamode; // From dv_elink of dv_elink.v
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wire [31:0] dut_dstaddr; // From dv_elink of dv_elink.v
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wire dut_failed; // From dv_elink of dv_elink.v
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wire dut_passed; // From dv_elink of dv_elink.v
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wire dut_rd_wait; // From dv_elink of dv_elink.v
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wire [31:0] dut_srcaddr; // From dv_elink of dv_elink.v
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wire dut_wr_wait; // From dv_elink of dv_elink.v
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wire dut_write; // From dv_elink of dv_elink.v
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// End of automatics
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//dut
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dv_elink dv_elink(/*AUTOINST*/
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// Outputs
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.dut_passed (dut_passed),
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.dut_failed (dut_failed),
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.dut_wr_wait (dut_wr_wait),
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.dut_rd_wait (dut_rd_wait),
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.dut_access (dut_access),
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.dut_write (dut_write),
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.dut_datamode (dut_datamode[1:0]),
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.dut_ctrlmode (dut_ctrlmode[3:0]),
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.dut_dstaddr (dut_dstaddr[31:0]),
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.dut_srcaddr (dut_srcaddr[31:0]),
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.dut_data (dut_data[31:0]),
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// Inputs
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.clk (clk),
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.reset (reset),
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.ext_access (ext_access),
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.ext_write (ext_write),
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.ext_datamode (ext_datamode[1:0]),
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.ext_ctrlmode (ext_ctrlmode[3:0]),
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.ext_dstaddr (ext_dstaddr[31:0]),
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.ext_data (ext_data[31:0]),
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.ext_srcaddr (ext_srcaddr[31:0]),
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.ext_wr_wait (ext_wr_wait),
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.ext_rd_wait (ext_rd_wait));
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endmodule // dv_elink_tb
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@ -8,11 +8,10 @@ module OBUFTDS (/*AUTOARG*/
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parameter IOSTANDARD=0;
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parameter SLEW=0;
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input I;
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input T;
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output O;
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output OB;
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input I; //input
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input T; //tristate signal
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output O; //output
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output OB; //output_bar
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assign O = T ? 1'bz : I;
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assign OB = T ? 1'bz : ~I;
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@ -5,19 +5,37 @@ module ODDR (/*AUTOARG*/
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C, CE, D1, D2, R, S
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);
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parameter DDR_CLK_EDGE=0;
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parameter INIT=0;
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parameter SRTYPE=0;
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parameter DDR_CLK_EDGE=0; //clock recovery mode
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parameter INIT=0; //Q init value
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parameter SRTYPE=0;//"SYNC", "ASYNC"
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input C;
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input CE;
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input D1;
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input D2;
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input R;
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input S;
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output Q;
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input C; // Clock input
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input CE; // Clock enable input
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input D1; // Data input1
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input D2; // Data input2
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input R; // Reset (depends on SRTYPE)
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input S; // Active high asynchronous pin
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output Q; // Data Output that connects to the IOB pad
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assign Q=1'b0;
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reg Q1,Q2;
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//Generate different logic based on parameters
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//Only doing same edge and async reset for now
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always @ (posedge C or posedge R)
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if (R)
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Q1 <= 1'b0;
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else
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Q1 <= D1;
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always @ (posedge C or posedge R)
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if (R)
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Q2 <= 1'b0;
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else
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Q2 <= D2;
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assign Q = C ? Q1 : Q2;
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endmodule // ODDR
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