Xilinx models

-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench

elink/dv/dv_elink_tb.v

@@ -31,8 +31,13 @@ module dv_elink_tb();
 	  clk      = 1'b0;
 	  datamode = 2'b11;	
 	#400 
-          //Setting config clocks to higher value to speed sims
+          //clock config
           dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0066;
+          //tx config 
+   	  dv_elink.elink.ecfg.ecfg_tx_reg[8:0]   = 9'h001;
+          //rx config
+	  dv_elink.elink.ecfg.ecfg_tx_reg[4:0]   = 5'h01;
+	 
 	  reset    = 1'b0;    // at time 100 release reset
 	#1000
           

stubs/hdl/OBUFTDS.v

@@ -8,11 +8,10 @@ module OBUFTDS (/*AUTOARG*/
    parameter IOSTANDARD=0;
    parameter SLEW=0;
    
-
+   input I;    //input
-   input I;
+   input T;    //tristate signal
-   input T;
+   output O;   //output
-   output O;
+   output OB;  //output_bar
-   output OB;
 
    assign O  = T ? 1'bz : I;
    assign OB = T ? 1'bz : ~I;

stubs/hdl/ODDR.v

@@ -5,19 +5,37 @@ module ODDR (/*AUTOARG*/
    C, CE, D1, D2, R, S
    );
 
-   parameter DDR_CLK_EDGE=0;
+   parameter DDR_CLK_EDGE=0; //clock recovery mode
-   parameter INIT=0;
+   parameter INIT=0; //Q init value
-   parameter SRTYPE=0;
+   parameter SRTYPE=0;//"SYNC", "ASYNC"
    
-   input C;
+   input C;  // Clock input
-   input CE;
+   input CE; // Clock enable input
-   input D1;
+   input D1; // Data input1
-   input D2;
+   input D2; // Data input2
-   input R;
+   input R;  // Reset (depends on SRTYPE)
-   input S;
+   input S;  // Active high asynchronous pin
-   output Q;
+   output Q; // Data Output that connects to the IOB pad
 
-   assign Q=1'b0;
+   reg 	  Q1,Q2;
+
+   //Generate different logic based on parameters
+
+   //Only doing same edge and async reset for now   
+   
+   always @ (posedge C or posedge R)
+     if (R)
+       Q1 <= 1'b0;
+     else
+       Q1 <= D1;
+
+   always @ (posedge C or posedge R)
+     if (R)
+       Q2 <= 1'b0;
+     else
+       Q2 <= D2;
+   
+   assign Q = C ? Q1 : Q2;
       
 endmodule // ODDR