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Making FIFO/memories easier to use

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-WIDTH/DEPTH parameters
-Removing references to "clean" in ifdefs
This commit is contained in:
Andreas Olofsson 2015-05-07 23:50:34 -04:00
parent dc8cb83268
commit b2b7f96e86
5 changed files with 131 additions and 124 deletions
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68
emailbox/hdl/emailbox.v
View File

@ -27,13 +27,15 @@ module emailbox (/*AUTOARG*/
mi_addr, mi_din
);
parameter DW = 32; //data width of fifo
parameter AW = 32; //data width of fifo
parameter PW = 104; //packet size
parameter RFAW = 6; //address bus width
parameter GROUP = 4'h0; //address map group
parameter ID = 12'h000; //link id
parameter DW = 32; //data width of fifo
parameter AW = 32; //data width of fifo
parameter PW = 104; //packet size
parameter RFAW = 6; //address bus width
parameter ID = 12'h000; //link id
parameter WIDTH = 104;
parameter DEPTH = 16;
/*****************************/
/*RESET */
/*****************************/
@ -71,14 +73,14 @@ module emailbox (/*AUTOARG*/
/*****************************/
/*WIRES */
/*****************************/
wire mailbox_read;
wire mi_rd;
wire [2*DW-1:0] mailbox_fifo_data;
wire mailbox_empty;
wire mailbox_pop;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh__write;
wire mailbox_read;
wire mi_rd;
wire [WIDTH-1:0] mailbox_fifo_data;
wire mailbox_empty;
wire mailbox_pop;
wire [31:0] emesh_addr;
wire [63:0] emesh_din;
wire emesh__write;
/*****************************/
/*WRITE TO FIFO */
@ -106,7 +108,8 @@ module emailbox (/*AUTOARG*/
if(mi_rd)
case(mi_addr[RFAW+1:2])
`E_MAILBOXLO: mi_dout[63:0] <= mailbox_fifo_data[63:0];
`E_MAILBOXHI: mi_dout[63:0] <= {mailbox_fifo_data[2*DW-1:DW],mailbox_fifo_data[2*DW-1:DW]};
`E_MAILBOXHI: mi_dout[63:0] <= {mailbox_fifo_data[2*DW-1:DW],
mailbox_fifo_data[2*DW-1:DW]};
default: mi_dout[63:0] <= 64'd0;
endcase // case (mi_addr[RFAW-1:2])
else
@ -120,21 +123,26 @@ module emailbox (/*AUTOARG*/
//BUG! This fifo is currently hard coded to 32 entries
//Should be parametrized to up to 4096 entries
fifo_async #(.DW(64), .AW(5)) fifo(// Outputs
.dout (mailbox_fifo_data[2*DW-1:0]),
.empty (mailbox_empty),
.full (mailbox_full),
.prog_full (),
.valid(),
//Read Port
.rd_en (mailbox_pop),
.rd_clk (rd_clk),
//Write Port
.din (emesh_din[63:0]),
.wr_en (emesh_write),
.wr_clk (wr_clk),
.reset (reset)
);
defparam fifo.WIDTH = WIDTH;
defparam fifo.DEPTH = DEPTH;
fifo_async fifo(// Outputs
.dout (mailbox_fifo_data[WIDTH-1:0]),
.empty (mailbox_empty),
.full (mailbox_full),
.prog_full (),
.valid(),
//Read Port
.rd_en (mailbox_pop),
.rd_clk (rd_clk),
//Write Port
.din ({40'b0,emesh_din[63:0]}),
.wr_en (emesh_write),
.wr_clk (wr_clk),
.wr_rst (reset),
.rd_rst (reset)
);
endmodule // emailbox

99
memory/hdl/fifo_async.v
View File

@ -4,68 +4,67 @@ module fifo_async
// Outputs
full, prog_full, dout, empty, valid,
// Inputs
reset, wr_clk, rd_clk, wr_en, din, rd_en
wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104;
parameter AW = 2;
parameter WIDTH = 104; //FIFO width
parameter DEPTH = 16; //FIFO depth
//##########
//# RESET/CLOCK
//##########
input reset; //asynchronous reset
input wr_rst; //write reset
input rd_rst; //read reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
input wr_en;
input [WIDTH-1:0] din;
output full;
output prog_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
reg valid;
input rd_en;
output [WIDTH-1:0] dout;
output empty;
output valid;
`ifdef TARGET_CLEAN
//Wires
wire [DW/8-1:0] wr_vec;
wire [AW:0] wr_rd_gray_pointer;
wire [AW:0] rd_wr_gray_pointer;
wire [AW:0] wr_gray_pointer;
wire [AW:0] rd_gray_pointer;
wire [AW-1:0] rd_addr;
wire [AW-1:0] wr_addr;
parameter AW = $clog2(DEPTH); //FIFO address width (for model)
assign wr_vec[DW/8-1:0] = {(DW/8){wr_en}};
//Wires
wire [WIDTH/8-1:0] wr_vec;
wire [AW:0] wr_rd_gray_pointer;
wire [AW:0] rd_wr_gray_pointer;
wire [AW:0] wr_gray_pointer;
wire [AW:0] rd_gray_pointer;
wire [AW-1:0] rd_addr;
wire [AW-1:0] wr_addr;
reg valid;
assign wr_vec[WIDTH/8-1:0] = {(WIDTH/8){wr_en}};
//Valid data at output
always @ (posedge rd_clk or posedge reset)
if(reset)
always @ (posedge rd_clk or posedge rd_rst)
if(rd_rst)
valid <=1'b0;
else
valid <= rd_en;
memory_dp #(.DW(DW),.AW(AW)) memory_dp (
memory_dp #(.FW(WIDTH),.AW(AW)) memory_dp (
// Outputs
.rd_data (dout[DW-1:0]),
.rd_data (dout[WIDTH-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_en (wr_vec[DW/8-1:0]),
.wr_en (wr_vec[WIDTH/8-1:0]),
.wr_addr (wr_addr[AW-1:0]),
.wr_data (din[DW-1:0]),
.wr_data (din[WIDTH-1:0]),
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]));
@ -77,7 +76,7 @@ module fifo_async
.rd_addr (rd_addr[AW-1:0]),
.rd_gray_pointer(rd_gray_pointer[AW:0]),
// Inputs
.reset (reset),
.reset (rd_rst),
.rd_clk (rd_clk),
.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
.rd_read (rd_en));
@ -90,7 +89,7 @@ module fifo_async
.wr_addr (wr_addr[AW-1:0]),
.wr_gray_pointer (wr_gray_pointer[AW:0]),
// Inputs
.reset (reset),
.reset (wr_rst),
.wr_clk (wr_clk),
.wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
.wr_write (wr_en));
@ -98,22 +97,36 @@ module fifo_async
synchronizer #(.DW(AW+1)) rd2wr_sync (.out (wr_rd_gray_pointer[AW:0]),
.in (rd_gray_pointer[AW:0]),
.reset (reset),
.reset (wr_rst),
.clk (wr_clk));
synchronizer #(.DW(AW+1)) wr2rd_sync (.out (rd_wr_gray_pointer[AW:0]),
.in (wr_gray_pointer[AW:0]),
.reset (reset),
.reset (rd_rst),
.clk (rd_clk));
`elsif TARGET_XILINX
generate
if((WIDTH==104) & (DEPTH==16))
fifo_async_104x16 fifo_async_104x16 (
.wr_clk(wr_clk),
.wr_rst(wr_rst),
.rd_clk(rd_clk),
.rd_rst(rd_rst),
.din(din[WIDTH-1:0]),
.wr_en(wr_en),
.rd_en(rd_en),
.dout(dout[WIDTH-1:0]),
.full(full),
.empty(empty),
.valid(valid)
);
endgenerate
`endif // !`elsif TARGET_XILINX
`elsif TARGET_XILINX
//insert generate FIFO
`endif // `ifdef TARGET_CLEAN
endmodule // fifo_async
// Local Variables:

72
memory/hdl/fifo_cdc.v
View File

@ -11,39 +11,37 @@ module fifo_cdc (/*AUTOARG*/
clk_in, clk_out, reset, access_in, packet_in, wait_in
);
parameter FD = 16; //minimum depth
parameter AW = $clog2(FD);
parameter DW = 104;
parameter WIDTH = 104;
parameter DEPTH = 16;
/********************************/
/*Clocks/reset */
/********************************/
input clk_in;
input clk_out;
input reset;
input clk_in;
input clk_out;
input reset;
/********************************/
/*Input Packet*/
/********************************/
input access_in;
input [DW-1:0] packet_in;
output wait_out;
input access_in;
input [WIDTH-1:0] packet_in;
output wait_out;
/********************************/
/*Register RD/WR Packet to ERX*/
/********************************/
output access_out;
output [DW-1:0] packet_out;
input wait_in;
output access_out;
output [WIDTH-1:0] packet_out;
input wait_in;
//Local wires
wire wr_en;
wire rd_en;
wire empty;
wire full;
reg access_out;
wire wr_en;
wire rd_en;
wire empty;
wire full;
reg access_out;
assign wr_en = access_in & ~full;
assign rd_en = ~empty & ~wait_in;
assign wait_out = full;
@ -56,21 +54,25 @@ module fifo_cdc (/*AUTOARG*/
access_out <=rd_en;
//Read response fifo (from master)
fifo_async #(.DW(DW), .AW(5)) fifo(
.prog_full (),
.full (full),
// Outputs
.dout (packet_out[DW-1:0]),
.empty (empty),
.valid (),
// Inputs
.reset (reset),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en)
);
defparam fifo.WIDTH=104;
defparam fifo.DEPTH=16;
fifo_async fifo(
.prog_full (),
.full (full),
// Outputs
.dout (packet_out[WIDTH-1:0]),
.empty (empty),
.valid (),
// Inputs
.wr_rst (reset),
.rd_rst (reset),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[WIDTH-1:0]),
.rd_en (rd_en)
);
endmodule // fifo_cdc

8
memory/hdl/memory_dp.v
View File

@ -34,8 +34,6 @@ module memory_dp(/*AUTOARG*/
//SIMPLE MEMORY MODEL
//////////////////////
`ifdef TARGET_CLEAN
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
@ -55,12 +53,6 @@ module memory_dp(/*AUTOARG*/
end
end
endgenerate
`elsif TARGET_XILINX
//instantiate XILINX BRAM (based on parameter size)
`elsif TARGET_ALTERA
`endif
endmodule // memory_dp

8
memory/hdl/memory_sp.v
View File

@ -26,8 +26,6 @@ module memory_sp(/*AUTOARG*/
input [DW-1:0] din; //data input
output [DW-1:0] dout;//data output
`ifdef TARGET_CLEAN
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
reg [DW-1:0] dout;
@ -48,12 +46,6 @@ module memory_sp(/*AUTOARG*/
end
end
endgenerate
`elsif TARGET_XILINX
//instantiate XILINX BRAM (based on parameter size)
`elsif TARGET_ALTERA
//instantiate ALTERA BRAM (based on paremeter size)
`endif
endmodule // memory_dp