From b741fcb3a9d6df557e9bf264e5b69ed175c96074 Mon Sep 17 00:00:00 2001
From: aolofsson <andreas@zeroasic.com>
Date: Thu, 29 Sep 2022 22:21:04 -0400
Subject: [PATCH] Adding sc place holder

---
 stdlib/stdlib.py | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 stdlib/stdlib.py

diff --git a/stdlib/stdlib.py b/stdlib/stdlib.py
new file mode 100644
index 0000000..af32e46
--- /dev/null
+++ b/stdlib/stdlib.py
@@ -0,0 +1,35 @@
+import sys
+import os
+import siliconcompiler
+
+def main():
+
+    progname = "oh"
+    description = """
+    --------------------------------------------------------------
+    App for building the ebrick.
+    """
+
+    UNSET_DESIGN = '  unset  '
+    chip = siliconcompiler.Chip(UNSET_DESIGN)
+
+    chip.create_cmdline(progname,
+                    switchlist=['-target', '-design'],
+                    description=description)
+
+    # Set default flow
+    if not chip.get('option', 'target'):
+        chip.load_target("freepdk45_demo")
+
+
+
+    chip.set('input', 'verilog', f"rtl/{chip.get('design')}.v")
+    chip.add('option', 'ydir', 'rtl')
+    chip.set('option', 'quiet', True)
+    chip.set('option', 'steplist', ['import','syn'])
+    # Run through the flow
+    chip.run()
+
+#########################
+if __name__ == "__main__":
+    sys.exit(main())