FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

Wrong bus width (just cleanup..)

Browse Source
This commit is contained in:
aolofsson 2014-12-15 15:26:07 -05:00
parent 1346c02803
commit b83ef81db6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
erx/hdl/erx_protocol.v
View File

@ -138,7 +138,7 @@ module erx_protocol (/*AUTOARG*/
rxactive_in <= 1'b1;
end else begin
rxalign_in <= 3'd0; // No edge
rxactive_in <= 3'd0;
rxactive_in <= 1'd0;
end
end // always @ ( posedge rxlclk_p )