diff --git a/elink/dv/dv_elink.v b/elink/dv/dv_elink.v index fc20dee..593988d 100644 --- a/elink/dv/dv_elink.v +++ b/elink/dv/dv_elink.v @@ -41,8 +41,9 @@ module dv_elink(/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [11:0] chipid; // From elink2 of axi_elink.v - wire [11:0] elink0_chipid; // From elink0 of elink.v + wire [11:0] e_chipid; // From elink2 of axi_elink.v + wire e_resetb; // From eclocks of eclocks.v + wire [11:0] elink0_e_chipid; // From elink0 of elink.v wire elink0_elink_en; // From elink0 of elink.v wire elink0_mailbox_full; // From elink0 of elink.v wire elink0_mailbox_not_empty;// From elink0 of elink.v @@ -66,7 +67,7 @@ module dv_elink(/*AUTOARG*/ wire elink0_txrd_wait; // From elink0 of elink.v wire elink0_txrr_wait; // From elink0 of elink.v wire elink0_txwr_wait; // From elink0 of elink.v - wire [11:0] elink1_chipid; // From elink1 of elink.v + wire [11:0] elink1_e_chipid; // From elink1 of elink.v wire elink1_elink_en; // From elink1 of elink.v wire elink1_mailbox_full; // From elink1 of elink.v wire elink1_mailbox_not_empty;// From elink1 of elink.v @@ -244,8 +245,8 @@ module dv_elink(/*AUTOARG*/ eclocks eclocks (.sys_clk (clk), .elink_en (elink0_elink_en), - .cclk_p (), - .cclk_n (), + .e_cclk_p (), + .e_cclk_n (), .rx_clkin (rx_lclk_pll), /*AUTOINST*/ // Outputs @@ -256,7 +257,7 @@ module dv_elink(/*AUTOARG*/ .rx_lclk_div4 (rx_lclk_div4), .rx_ref_clk (rx_ref_clk), .elink_reset (elink_reset), - .chip_resetb (chip_resetb), + .e_resetb (e_resetb), // Inputs .reset (reset)); @@ -328,7 +329,7 @@ module dv_elink(/*AUTOARG*/ .txo_frame_n (elink0_txo_frame_n), // Templated .txo_data_p (elink0_txo_data_p[7:0]), // Templated .txo_data_n (elink0_txo_data_n[7:0]), // Templated - .chipid (elink0_chipid[11:0]), // Templated + .e_chipid (elink0_e_chipid[11:0]), // Templated .elink_en (elink0_elink_en), // Templated .rxwr_access (elink0_rxwr_access), // Templated .rxwr_packet (elink0_rxwr_packet[PW-1:0]), // Templated @@ -398,7 +399,7 @@ module dv_elink(/*AUTOARG*/ .txo_frame_n (elink1_txo_frame_n), // Templated .txo_data_p (elink1_txo_data_p[7:0]), // Templated .txo_data_n (elink1_txo_data_n[7:0]), // Templated - .chipid (elink1_chipid[11:0]), // Templated + .e_chipid (elink1_e_chipid[11:0]), // Templated .elink_en (elink1_elink_en), // Templated .rxwr_access (elink1_rxwr_access), // Templated .rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated @@ -485,9 +486,9 @@ module dv_elink(/*AUTOARG*/ .txi_wr_wait_n (rxo_wr_wait_n), .txi_rd_wait_p (rxo_rd_wait_p), .txi_rd_wait_n (rxo_rd_wait_n), - .chip_resetb (chip_resetb), - .cclk_p (cclk_p), - .cclk_n (cclk_n), + .e_resetb (chip_resetb), + .e_cclk_p (cclk_p), + .e_cclk_n (cclk_n), /*AUTOINST*/ // Outputs .rxo_wr_wait_p (rxo_wr_wait_p), @@ -500,7 +501,7 @@ module dv_elink(/*AUTOARG*/ .txo_frame_n (txo_frame_n), .txo_data_p (txo_data_p[7:0]), .txo_data_n (txo_data_n[7:0]), - .chipid (chipid[11:0]), + .e_chipid (e_chipid[11:0]), .mailbox_not_empty (mailbox_not_empty), .mailbox_full (mailbox_full), .m_axi_awid (s_axi_awid[IDW-1:0]), // Templated diff --git a/elink/hdl/axi_elink.v b/elink/hdl/axi_elink.v index bee1b95..3e3c5dd 100644 --- a/elink/hdl/axi_elink.v +++ b/elink/hdl/axi_elink.v @@ -2,16 +2,16 @@ module axi_elink(/*AUTOARG*/ // Outputs rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, - txo_data_n, chipid, chip_resetb, cclk_p, cclk_n, mailbox_not_empty, - mailbox_full, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, - m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, - m_axi_awqos, m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, - m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, - m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, - m_axi_arcache, m_axi_arprot, m_axi_arqos, m_axi_arvalid, - m_axi_rready, s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, - s_axi_bvalid, s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, - s_axi_rvalid, s_axi_wready, + txo_data_n, e_chipid, e_resetb, e_cclk_p, e_cclk_n, + mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr, + m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, + m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid, + m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready, + m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, + m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos, + m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready, + s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata, + s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready, // Inputs reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n, @@ -59,15 +59,15 @@ module axi_elink(/*AUTOARG*/ /********************************/ /*EPIPHANY INTERFACE (I/O PINS) */ /********************************/ - output [11:0] chipid; //chip id strap pins for Epiphany - output chip_resetb; //chip reset for Epiphany (active low) - output cclk_p,cclk_n; //high speed clock (up to 1GHz) to Epiphany + output [11:0] e_chipid; //chip id strap pins for Epiphany + output e_resetb; //chip reset for Epiphany (active low) + output e_cclk_p,e_cclk_n; //high speed clock (up to 1GHz) to Epiphany /*****************************/ /*MAILBOX (interrupts) */ /*****************************/ - output mailbox_not_empty; - output mailbox_full; + output mailbox_not_empty; + output mailbox_full; //######################## //AXI MASTER INTERFACE @@ -236,7 +236,7 @@ module axi_elink(/*AUTOARG*/ .txo_frame_n (txo_frame_n), .txo_data_p (txo_data_p[7:0]), .txo_data_n (txo_data_n[7:0]), - .chipid (chipid[11:0]), + .e_chipid (e_chipid[11:0]), .elink_en (elink_en), .rxwr_access (rxwr_access), .rxwr_packet (rxwr_packet[PW-1:0]), @@ -291,10 +291,10 @@ module axi_elink(/*AUTOARG*/ .rx_lclk (rx_lclk), .rx_lclk_div4 (rx_lclk_div4), .rx_ref_clk (rx_ref_clk), - .cclk_p (cclk_p), - .cclk_n (cclk_n), + .e_cclk_p (e_cclk_p), + .e_cclk_n (e_cclk_n), .elink_reset (elink_reset), - .chip_resetb (chip_resetb), + .e_resetb (e_resetb), // Inputs .reset (reset), .elink_en (elink_en), diff --git a/elink/hdl/ecfg_elink.v b/elink/hdl/ecfg_elink.v index d2b95b1..77bf76d 100644 --- a/elink/hdl/ecfg_elink.v +++ b/elink/hdl/ecfg_elink.v @@ -6,7 +6,7 @@ module ecfg_elink (/*AUTOARG*/ // Outputs - txwr_gated_access, elink_en, clk_config, chipid, + txwr_gated_access, elink_en, clk_config, e_chipid, // Inputs txwr_access, txwr_packet, clk, reset ); @@ -38,7 +38,7 @@ module ecfg_elink (/*AUTOARG*/ /******************************/ output elink_en; // elink master enable output [15:0] clk_config; // clock settings (for pll) - output [11:0] chipid; // chip-id for Epiphany + output [11:0] e_chipid; // chip-id for Epiphany /*------------------------CODE BODY---------------------------------------*/ @@ -126,7 +126,7 @@ module ecfg_elink (/*AUTOARG*/ else if (ecfg_chipid_write) ecfg_chipid_reg[11:0] <= mi_din[11:0]; - assign chipid[11:0]=ecfg_chipid_reg[5:2]; + assign e_chipid[11:0]=ecfg_chipid_reg[5:2]; endmodule // ecfg_elink diff --git a/elink/hdl/eclocks.v b/elink/hdl/eclocks.v index 8b52d48..188c9e0 100644 --- a/elink/hdl/eclocks.v +++ b/elink/hdl/eclocks.v @@ -16,7 +16,7 @@ module eclocks (/*AUTOARG*/ // Outputs tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4, - rx_ref_clk, cclk_p, cclk_n, elink_reset, chip_resetb, + rx_ref_clk, e_cclk_p, e_cclk_n, elink_reset, e_resetb, // Inputs reset, elink_en, sys_clk, rx_clkin ); @@ -58,11 +58,11 @@ module eclocks (/*AUTOARG*/ output rx_ref_clk; // clock for idelay element //Epiphany "free running" clock - output cclk_p, cclk_n; + output e_cclk_p, e_cclk_n; //Reset output elink_reset; // reset for elink logic & IO - output chip_resetb; // reset fpr Epiphany chip + output e_resetb; // reset fpr Epiphany chip //########################### // RESET STATE MACHINE @@ -136,9 +136,9 @@ module eclocks (/*AUTOARG*/ (reset_state[2:0]==`STOP_PLL) | (reset_state[2:0]==`START_EPIPHANY); - assign chip_resetb = (reset_state[2:0]==`START_EPIPHANY) | - (reset_state[2:0]==`HOLD_IT) | - (reset_state[2:0]==`ACTIVE); + assign e_resetb = (reset_state[2:0]==`START_EPIPHANY) | + (reset_state[2:0]==`HOLD_IT) | + (reset_state[2:0]==`ACTIVE); assign elink_reset = (reset_state[2:0]!=`ACTIVE); @@ -218,8 +218,8 @@ module eclocks (/*AUTOARG*/ .CLKINSTOPPED() ); - OBUFDS cclk_obuf (.O (cclk_p), - .OB (cclk_n), + OBUFDS cclk_obuf (.O (e_cclk_p), + .OB (e_cclk_n), .I (cclk) ); diff --git a/elink/hdl/elink.v b/elink/hdl/elink.v index c033a77..510d918 100644 --- a/elink/hdl/elink.v +++ b/elink/hdl/elink.v @@ -2,9 +2,10 @@ module elink(/*AUTOARG*/ // Outputs rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, - txo_data_p, txo_data_n, chipid, elink_en, rxwr_access, rxwr_packet, - rxrd_access, rxrd_packet, rxrr_access, rxrr_packet, txwr_wait, - txrd_wait, txrr_wait, mailbox_not_empty, mailbox_full, timeout, + txo_data_p, txo_data_n, e_chipid, elink_en, rxwr_access, + rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet, + txwr_wait, txrd_wait, txrr_wait, mailbox_not_empty, mailbox_full, + timeout, // Inputs reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4, rx_ref_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, @@ -52,7 +53,7 @@ module elink(/*AUTOARG*/ /********************************/ /*EPIPHANY INTERFACE (I/O PINS) */ /********************************/ - output [11:0] chipid; // chip id strap pins for epiphany + output [11:0] e_chipid; // chip id strap pins for epiphany output elink_en; // master enable for elink/epiphany /*****************************/ @@ -138,7 +139,7 @@ module elink(/*AUTOARG*/ .txwr_gated_access (txwr_gated_access), .elink_en (elink_en), .clk_config (clk_config[15:0]), - .chipid (chipid[11:0]), + .e_chipid (e_chipid[11:0]), // Inputs .txwr_access (txwr_access), .txwr_packet (txwr_packet[PW-1:0]),