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Adding skeleton for adi sdr design

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Now need to integrate elink in this
This commit is contained in:
Andreas Olofsson 2015-11-11 00:42:14 -05:00
parent 9feaa36dce
commit bb084f1670
4 changed files with 1231 additions and 0 deletions
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5
parallella/fpga/sdr_fmcomms/build.sh Executable file
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#!/bin/bash
vivado -mode batch -source run.tcl
rm system_wrapper.bit.bin bit2bin.bin
bootgen -image bit2bin.bif -split bin
cp system_wrapper.bit.bin parallella.bit.bin

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parallella/fpga/sdr_fmcomms/run.tcl Normal file
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#STEP1: DEFINE KEY PARAMETERS
source ./system_params.tcl
#STEP2: CREATE PROJECT AND READ IN FILES
source ../../../common/fpga/system_init.tcl
#STEP 3 (OPTIONAL): EDIT system.bd in VIVADO gui, then go to STEP 4.
##...
#STEP 4: SYNTEHSIZE AND CREATE BITSTRAM
source ../../../common/fpga/system_build.tcl

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parallella/fpga/sdr_fmcomms/system_bd.tcl Normal file
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parallella/fpga/sdr_fmcomms/system_params.tcl Normal file
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#Design name ("system" recommended)
set design system
#Project directory ("." recommended)
set projdir ./
#Device name
set partname "xc7z020clg400-1"
#Paths to all IP blocks to use in Vivado "system.bd"
set ip_repos [list "../parallella_base"]
#All source files
set hdl_files []
#All constraints files
set constraints_files [list \
../parallella_timing.xdc \
../parallella_io.xdc \
../parallella_7020_io.xdc \
]