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Fixed testbench bug (copy paste, RX not enabled)...

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This commit is contained in:
Andreas Olofsson 2015-04-17 10:08:17 -04:00
parent dca611c5ba
commit bd90cc8f92
4 changed files with 14 additions and 10 deletions
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3
elink/dv/dv_elink_tb.v
View File

@ -36,11 +36,10 @@ module dv_elink_tb();
//tx config (enable)
dv_elink.elink.ecfg.ecfg_tx_reg[8:0] = 9'h001;
//rx config (enable)
dv_elink.elink.ecfg.ecfg_tx_reg[4:0] = 5'h01;
dv_elink.elink.ecfg.ecfg_rx_reg[4:0] = 5'h01;
reset = 1'b0; // at time 100 release reset
#1000
go = 1'b1;
#2000
datamode = 2'b10;

1
elink/hdl/erx.v
View File

@ -289,6 +289,7 @@ module erx (/*AUTOARG*/
.emmu_data_out (emmu_data[DW-1:0]), // Templated
// Inputs
.clk (rx_lclk_div4), // Templated
.reset (reset),
.mmu_en (ecfg_rx_mmu_enable), // Templated
.mi_clk (mi_clk),
.mi_en (mi_en),

6
elink/hdl/erx_io.v
View File

@ -266,9 +266,9 @@ module erx_io (/*AUTOARG*/
always @ (posedge rx_lclk_div4 or posedge rxreset)
begin
if(rxreset)
rxenb_sync <= 'd0;
rxenb_sync[1:0] <= 'd0;
else
rxenb_sync <= {1'b1, rxenb_sync[1]};
rxenb_sync[1:0] <= {1'b1, rxenb_sync[1]};
end
always @ (posedge rx_lclk_div4)
@ -276,7 +276,7 @@ module erx_io (/*AUTOARG*/
rxgpio_sync <= {ecfg_rx_gpio_enable, rxgpio_sync[1]};
rx_data_reg[63:0] <= rx_data_des[63:0];
rx_data_par[63:0] <= rx_data_reg[63:0];
rx_frame_reg[7:0] <= rx_frame_des & {8{rxenb}} & {8{~rxgpio}};
rx_frame_reg[7:0] <= rx_frame_des[7:0] & {8{rxenb}} & {8{~rxgpio}};
rx_frame_par[7:0] <= rx_frame_reg[7:0];
end

14
emmu/hdl/emmu.v
View File

@ -11,14 +11,14 @@
#
############################################################################
*/
module emmu (/*AUTOARG*/
// Outputs
mi_dout, emmu_access_out, emmu_write_out, emmu_datamode_out,
emmu_ctrlmode_out, emmu_dstaddr_out, emmu_srcaddr_out,
emmu_data_out,
// Inputs
clk, mmu_en, mi_clk, mi_en, mi_we, mi_addr, mi_din,
clk, reset, mmu_en, mi_clk, mi_en, mi_we, mi_addr, mi_din,
emesh_access_in, emesh_write_in, emesh_datamode_in,
emesh_ctrlmode_in, emesh_dstaddr_in, emesh_srcaddr_in,
emesh_data_in
@ -34,6 +34,7 @@ module emmu (/*AUTOARG*/
/*DATAPATH CLOCk */
/*****************************/
input clk;
input reset;
/*****************************/
/*MMU LOOKUP DATA */
@ -101,6 +102,8 @@ module emmu (/*AUTOARG*/
//write data
assign emmu_wr_data[63:0] = {mi_din[31:0], mi_din[31:0]};
`ifdef TARGET_XILINX
memory_dp_48x4096 memory_dp_48x4096(
//write (portA)
@ -121,15 +124,14 @@ module emmu (/*AUTOARG*/
assign emmu_lookup_data[47:0]=48'b0;
`endif // !`ifdef TARGET_XILINX
/*****************************/
/*EMESH OUTPUT TRANSACTION */
/*****************************/
//pipeline to compensate for table lookup pipeline
//assumes one cycle memory access!
always @ (posedge clk)
always @ (posedge clk)
emmu_access_out <= emesh_access_in;
always @ (posedge clk)
@ -147,6 +149,8 @@ module emmu (/*AUTOARG*/
emmu_dstaddr_reg[19:0]} :
{32'b0,emmu_dstaddr_reg[31:0]};
endmodule // emmu
// Local Variables:
// verilog-library-directories:("." "../../stubs/hdl")