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Refactoring (methodology)
This commit is contained in:
Andreas Olofsson
parent
c1da2531e6
commit
becff479ca
@ -53,8 +53,7 @@ module etx_core(/*AUTOARG*/
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire burst_enable; // From etx_cfg of etx_cfg.v
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@ -85,42 +84,39 @@ module etx_core(/*AUTOARG*/
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wire tx_enable; // From etx_cfg of etx_cfg.v
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// End of automatics
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/************************************************************/
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/*ELINK TRANSMIT ARBITER */
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/*-arbitrates between the wr,rr, and rd packets */
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/* */
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/************************************************************/
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//##################################################################
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//# ARBITER (SELECT BETWEEN TX, RX, RR)
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//##################################################################
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defparam etx_arbiter.ID=ID;
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etx_arbiter etx_arbiter (
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/*AUTOINST*/
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// Outputs
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.etx_access (etx_access),
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.etx_rr (etx_rr),
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.etx_packet (etx_packet[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_cfg_wait (etx_cfg_wait),
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.ctrlmode_bypass (ctrlmode_bypass),
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.ctrlmode (ctrlmode[3:0]));
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/************************************************************/
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/* REMAPPING (SHIFT) DESTINATION ADDRESS */
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/************************************************************/
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/*etx_remap AUTO_TEMPLATE (
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etx_arbiter #(.ID(ID))
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etx_arbiter (
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/*AUTOINST*/
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// Outputs
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.etx_access (etx_access),
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.etx_rr (etx_rr),
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.etx_packet (etx_packet[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_cfg_wait (etx_cfg_wait),
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.ctrlmode_bypass (ctrlmode_bypass),
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.ctrlmode (ctrlmode[3:0]));
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//##################################################################
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//# REMAPPING DESTINATION ADDRESS
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//##################################################################
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/*etx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_in (etx_\1[]),
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.emesh_\(.*\)_out (etx_remap_\1[]),
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.remap_en (remap_enable),
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@ -143,10 +139,11 @@ module etx_core(/*AUTOARG*/
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait));
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/************************************************************/
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/* EMMU */
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/************************************************************/
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//##################################################################
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//# TABLE LOOKUP ADDRESS TRANSLATION
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//##################################################################
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/*emmu AUTO_TEMPLATE (
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.emesh_\(.*\)_in (etx_remap_\1[]),
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.emesh_\(.*\)_out (emmu_\1[]),
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@ -164,8 +161,6 @@ module etx_core(/*AUTOARG*/
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);
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*/
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//TODO: Remove etx_rr, not needed?
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emmu etx_mmu (
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/*AUTOINST*/
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// Outputs
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@ -188,9 +183,10 @@ module etx_core(/*AUTOARG*/
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.emesh_wr_wait (etx_wr_wait)); // Templated
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/************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/************************************************************/
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//##################################################################
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//# ELINK PROTOCOL CONVERTER (104 bit-->64 bits)
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//##################################################################
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/*etx_protocol AUTO_TEMPLATE (
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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@ -198,33 +194,33 @@ module etx_core(/*AUTOARG*/
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.etx_wait (etx_wait),
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);
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*/
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defparam etx_protocol.ID=ID;
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etx_protocol etx_protocol (
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etx_protocol #(.ID(ID))
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etx_protocol (
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/*AUTOINST*/
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// Outputs
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.etx_rd_wait (etx_rd_wait), // Templated
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.etx_wr_wait (etx_wr_wait), // Templated
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.tx_burst (tx_burst),
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.tx_access (tx_access),
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.tx_data_slow (tx_data_slow[63:0]),
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.tx_frame_slow (tx_frame_slow[3:0]),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.etx_access (emmu_access), // Templated
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.etx_packet (emmu_packet[PW-1:0]), // Templated
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.tx_enable (tx_enable),
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.burst_enable (burst_enable),
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.gpio_data (gpio_data[8:0]),
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.gpio_enable (gpio_enable),
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.tx_rd_wait (tx_rd_wait),
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.tx_wr_wait (tx_wr_wait));
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// Outputs
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.etx_rd_wait (etx_rd_wait), // Templated
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.etx_wr_wait (etx_wr_wait), // Templated
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.tx_burst (tx_burst),
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.tx_access (tx_access),
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.tx_data_slow (tx_data_slow[63:0]),
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.tx_frame_slow (tx_frame_slow[3:0]),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.etx_access (emmu_access), // Templated
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.etx_packet (emmu_packet[PW-1:0]), // Templated
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.tx_enable (tx_enable),
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.burst_enable (burst_enable),
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.gpio_data (gpio_data[8:0]),
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.gpio_enable (gpio_enable),
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.tx_rd_wait (tx_rd_wait),
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.tx_wr_wait (tx_wr_wait));
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/************************************************************/
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/* CONFIGURATOIN PACKET */
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/************************************************************/
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//##################################################################
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//# Register interface for TX (or forward to RX)
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//##################################################################
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/*ecfg_if AUTO_TEMPLATE (
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.\(.*\)_in (etx_\1[]),
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.\(.*\)_out (etx_cfg_\1[]),
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@ -233,58 +229,53 @@ module etx_core(/*AUTOARG*/
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.wait_in (etx_cfg_wait),
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);
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*/
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ecfg_if #(.ID(ID),
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.RX(0))
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defparam etx_cfgif.RX = 0;
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defparam etx_cfgif.ID = ID;
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ecfg_if etx_cfgif (.mi_dout3 (64'b0),
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.mi_dout1 (64'b0),
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.mi_dma_en (),
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/*AUTOINST*/
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// Outputs
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.mi_mmu_en (mi_mmu_en),
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.mi_cfg_en (mi_cfg_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[63:0]),
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.access_out (etx_cfg_access), // Templated
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.packet_out (etx_cfg_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.access_in (etx_access), // Templated
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.packet_in (etx_packet[PW-1:0]), // Templated
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
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.wait_in (etx_cfg_wait)); // Templated
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etx_cfgif (.mi_dout3 (64'b0),
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.mi_dout1 (64'b0),
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.mi_dma_en (),
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/*AUTOINST*/
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// Outputs
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.mi_mmu_en (mi_mmu_en),
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.mi_cfg_en (mi_cfg_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[63:0]),
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.access_out (etx_cfg_access), // Templated
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.packet_out (etx_cfg_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.access_in (etx_access), // Templated
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.packet_in (etx_packet[PW-1:0]), // Templated
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
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.wait_in (etx_cfg_wait)); // Templated
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/************************************************************/
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/* ETX CONFIGURATION REGISTERS */
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/************************************************************/
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//##################################################################
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//# TX CONFIGURATION
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//##################################################################
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/*etx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
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.mi_en (mi_cfg_en),
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);
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*/
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//synchronizing signals from sys_clk fifo
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assign tx_status[15:0] = {5'b0,
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tx_burst,
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tx_rd_wait,
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tx_wr_wait,
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etx_rd_wait,
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etx_wr_wait,
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txrr_wait,
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txrd_wait,
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txwr_wait,
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txrr_full,
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txrd_full,
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txwr_full
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};
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//configer register file
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defparam etx_cfg.ID = ID;
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etx_cfg etx_cfg (
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etx_cfg etx_cfg (.tx_status ({5'b0,
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tx_burst,
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tx_rd_wait,
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tx_wr_wait,
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etx_rd_wait,
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etx_wr_wait,
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txrr_wait,
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txrd_wait,
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txwr_wait,
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txrr_full,
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txrd_full,
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txwr_full
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}),
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
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@ -303,7 +294,6 @@ module etx_core(/*AUTOARG*/
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[31:0]),
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.tx_status (tx_status[15:0]),
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.etx_access (etx_access),
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.etx_packet (etx_packet[PW-1:0]));
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