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Changing order of RAM array

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Andreas.Olofsson 2020-03-28 15:38:29 -04:00
parent 65aa1b061c
commit c271360709
1 changed files with 1 additions and 1 deletions
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common/hdl/oh_memory_ram.v
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@ -22,7 +22,7 @@ module oh_memory_ram # (parameter DW = 104, //memory width
input [DW-1:0] wr_din // data input input [DW-1:0] wr_din // data input
); );
reg [DW-1:0] ram [DEPTH-1:0]; reg [DW-1:0] ram [0:DEPTH-1];
integer i; integer i;
//registered read port //registered read port