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Cleaning up licenses for consistency
-All files still GPLv3 -Placed at the bottom of the file (I am tired of looking at them!)
This commit is contained in:
Andreas Olofsson
parent
18b2c489b0
commit
c41a0a8640
@ -27,3 +27,21 @@ module ereset (/*AUTOARG*/
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endmodule // ereset
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Roman Trogan <roman@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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@ -567,4 +567,21 @@ module esaxi (/*autoarg*/
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assign emrr_mux_data[31:0] = mi_rd_reg ? mi_dout[31:0] :
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emrr_data[31:0];
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endmodule
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endmodule // esaxi
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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@ -287,7 +287,8 @@ endmodule // etx_io
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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@ -1,25 +1,4 @@
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/*
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File: parallella_gpio_emio.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013-2014 Adapteva, Inc.
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Contributed by Fred Huettig
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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// Implements GPIO pins from the PS/EMIO
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// Works with 7010 (24 pins) or 7020 (48 pins) and
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@ -136,3 +115,25 @@ module parallella_gpio_emio
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endgenerate
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endmodule // parallella_gpio_emio
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/*
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File: parallella_gpio_emio.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013-2014 Adapteva, Inc.
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Contributed by Fred Huettig
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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@ -1,25 +1,4 @@
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/*
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File: parallella_i2c
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013-2015 Adapteva, Inc.
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Contributed by Fred Huettig
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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// Implements I2C from the Zynq PS
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@ -85,3 +64,25 @@ module parallella_i2c
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endmodule // parallella_i2c
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/*
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File: parallella_i2c
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013-2015 Adapteva, Inc.
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Contributed by Fred Huettig
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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@ -1,21 +1,3 @@
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module fifo_full_block (/*AUTOARG*/
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// Outputs
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wr_fifo_full, wr_fifo_progfull, wr_addr, wr_gray_pointer,
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@ -117,3 +99,21 @@ endmodule // fifo_full_block
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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@ -1,17 +1,4 @@
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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/*###########################################################################
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# Function: Single port memory wrapper
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@ -77,7 +64,20 @@ module memory_sp(/*AUTOARG*/
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endmodule // memory_dp
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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@ -1,30 +1,3 @@
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/*
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An OSERDESE2 is a device with an input register running on the rising edge of the CLKDIV
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clock and a loadable parallel-to-serial register running on the rising edges of the CLK clock. An
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internal state machine with the DATA_WIDTH parameter as set point makes sure the data from
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the parallel input register is transferred at the right moment into the parallel-to-serial register.
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An internal state machine controls the connection between the two registers. The state
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machine bounds CLK, CLKDIV, and the DATA_WITDH attribute to make sure data is always
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transferred from the parallel input register into the parallel-to-serial register at the correct
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moment.
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The parallel input register has no enable (OCE) or reset (RST). This means that as soon
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as a rising CLKDIV edge is applied, any data available on the input pins of the
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OSERDESE2 is loaded into the register.
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To prevent the OSERDESE2 from starting to generate unknown data immediately after
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release of the reset, keep the enable input deasserted for a number of CLKDIV clock
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cycles by using a LUT as programmable shift register (SRL32). The amount of clock
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cycles the enable input is held deasserted after releasing the reset is now programmable
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via the address input of the SRL32.
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*/
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module OSERDESE2 ( /*AUTOARG*/
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// Outputs
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OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ,
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@ -1,4 +1,3 @@
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module memory_dp_48x4096 (/*AUTOARG*/
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// Outputs
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doutb,
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