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Changing so basic elink unti is without AXI
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@ -224,26 +224,28 @@
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###INTERNAL STRUCTURE
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```
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elink - Top level level AXI elink peripheral
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emaxi - AXI master interface
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exaxi - AXI slave interface
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elink - Top level level AXI elink peripheral
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etx - Elink transmit block
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ecfg_tx - TX config
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etx_io - Converts packet to high speed serial
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etx_protocol - Creates an elink transaction packet
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etx_arbiter - Selects one of three AXI traffic sources (rd, wr, rr)
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s_rq_fifo - Read request fifo for slave AXI interface
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s_wr_fifo - Write request fifo for slave AXI interface
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m_rr_fifo - Read response fifo for master AXI interface
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erx - Elink receiver block
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etx_io - Converts serial packet received to parallel
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etx_protocol - Converts the elink packet to 104 bit emesh transaction
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etx_disty - Decodes emesh transaction and sends to AXI interface
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emmu - Translates the dstaddr of incoming transaction
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m_rq_fifo - Read request fifo for master AXI interface
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m_wr_fifo - Write request fifo for master AXI interface
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s_rr_fifo - Read response fifo for slave AXI interface
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ecfg - Configurationr register file for elink
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embox - Mail box (with interrupt output)
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txrd_fifo - Read request fifo for slave AXI interface
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txwr_fifo - Write request fifo for slave AXI interface
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txrr_fifo - Read response fifo for master AXI interface
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erx - Elink receiver block
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ecfg_rx - RX config
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etx_io - Converts serial packet received to parallel
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etx_protocol - Converts the elink packet to 104 bit emesh packet
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etx_disty - Distributes emesh packet to correct fifo
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emmu - Translates the dstaddr of incoming packet
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emailbox - Mailbox with interrupt output
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edma - Master DMA for rxrd_fifo
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rxrd_fifo - Read request fifo for master AXI interface
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rxwr_fifo - Write request fifo for master AXI interface
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rxrr_fifo - Read response fifo for slave AXI interface
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ecfg_base - General elink config
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eclocks - PLL/clock generator
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ereset - Reset generator
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@ -254,28 +256,16 @@ module elink(/*AUTOARG*/
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colid, rowid, chip_resetb, cclk_p, cclk_n, rxo_wr_wait_p,
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rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, txo_lclk_p,
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txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_data_n,
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m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
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m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
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m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
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m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
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m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
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m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
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s_axi_arready, s_axi_awready, s_axi_bid, s_axi_bresp, s_axi_bvalid,
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s_axi_rid, s_axi_rdata, s_axi_rlast, s_axi_rresp, s_axi_rvalid,
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s_axi_wready, embox_not_empty, embox_full,
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mailbox_not_empty, mailbox_full, rxwr_access, rxwr_packet,
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rxrd_access, rxrd_packet, rxrr_access, rxrr_packet, txwr_wait,
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txrd_wait, txrr_wait,
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// Inputs
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hard_reset, clkin, clkbypass, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, m_axi_aclk, m_axi_aresetn,
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m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid,
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m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast,
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m_axi_rvalid, s_axi_aclk, s_axi_aresetn, s_axi_arid, s_axi_araddr,
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s_axi_arburst, s_axi_arcache, s_axi_arlock, s_axi_arlen,
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s_axi_arprot, s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid,
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s_axi_awaddr, s_axi_awburst, s_axi_awcache, s_axi_awlock,
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s_axi_awlen, s_axi_awprot, s_axi_awqos, s_axi_awsize,
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s_axi_awvalid, s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata,
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s_axi_wlast, s_axi_wstrb, s_axi_wvalid
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txi_rd_wait_p, txi_rd_wait_n, rxwr_clk, rxwr_wait, rxrd_clk,
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rxrd_wait, rxrr_clk, rxrr_wait, txwr_clk, txwr_access, txwr_packet,
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txrd_clk, txrd_access, txrd_packet, txrr_clk, txrr_access,
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txrr_packet
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);
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parameter DEF_COREID = 12'h810;
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@ -287,14 +277,15 @@ module elink(/*AUTOARG*/
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parameter INC_PLL = 1; //include pll
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parameter INC_SPI = 1; //include spi block
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parameter ELINKID = 12'h810; //elink ID (used for registers)
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parameter PW = 104; //packet width
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/****************************/
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/*CLK AND RESET */
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/****************************/
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input hard_reset; // active high synhcronous hardware reset
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input clkin; // clock for pll
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input [2:0] clkbypass; // bypass clocks for elinks w/o pll
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// "advanced", tie to zero if not used
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input hard_reset; // active high synhcronous hardware reset
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input clkin; // clock for pll
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input [2:0] clkbypass; // bypass clocks for elinks w/o pll
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// "advanced", tie to zero if not used
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/********************************/
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/*EPIPHANY INTERFACE (I/O PINS) */
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@ -320,122 +311,52 @@ module elink(/*AUTOARG*/
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input txi_wr_wait_p,txi_wr_wait_n; //link tx write pushback input
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input txi_rd_wait_p,txi_rd_wait_n; //link tx read pushback input
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/*****************************/
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/*AXI master interface */
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/*****************************/
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//Clock and reset
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input m_axi_aclk; //axi master clock
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input m_axi_aresetn; //axi master reset (active low)
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//Write address channel
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output [IDW-1:0] m_axi_awid; // write address ID
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output [31 : 0] m_axi_awaddr; // master interface write address
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output [7 : 0] m_axi_awlen; // burst length.
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output [2 : 0] m_axi_awsize; // burst size.
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output [1 : 0] m_axi_awburst; // burst type.
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output [1:0] m_axi_awlock; // lock type
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output [3 : 0] m_axi_awcache; // memory type.
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output [2 : 0] m_axi_awprot; // protection type.
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output [3 : 0] m_axi_awqos; // quality of service
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output m_axi_awvalid; // write address valid
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input m_axi_awready; // write address ready
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//Write data channel
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output [IDW-1:0] m_axi_wid;
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output [63 : 0] m_axi_wdata; // master interface write data.
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output [7 : 0] m_axi_wstrb; // byte write strobes
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output m_axi_wlast; // indicates last transfer in a write burst.
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output m_axi_wvalid; // indicates data is ready to go
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input m_axi_wready; // indicates that the slave is ready for data
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//Write response channel
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input [IDW-1:0] m_axi_bid;
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input [1 : 0] m_axi_bresp; // status of the write transaction.
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input m_axi_bvalid; // channel is signaling a valid write response
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output m_axi_bready; // master can accept write response.
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//Read address channel
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output [IDW-1:0] m_axi_arid; // read address ID
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output [31 : 0] m_axi_araddr; // initial address of a read burst
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output [7 : 0] m_axi_arlen; // burst length
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output [2 : 0] m_axi_arsize; // burst size
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output [1 : 0] m_axi_arburst; // burst type
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output [1 : 0] m_axi_arlock; //lock type
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output [3 : 0] m_axi_arcache; // memory type
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output [2 : 0] m_axi_arprot; // protection type
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output [3 : 0] m_axi_arqos; //
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output m_axi_arvalid; // valid read address and control information
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input m_axi_arready; // slave is ready to accept an address
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//Read data channel
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input [IDW-1:0] m_axi_rid;
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input [63 : 0] m_axi_rdata; // master read data
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input [1 : 0] m_axi_rresp; // status of the read transfer
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input m_axi_rlast; // signals last transfer in a read burst
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input m_axi_rvalid; // signaling the required read data
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output m_axi_rready; // master can accept the readback data
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/*****************************/
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/*AXI slave interface */
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/*****************************/
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//Clock and reset
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input s_axi_aclk;
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input s_axi_aresetn;
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//Read address channel
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input [IDW-1:0] s_axi_arid; //write address ID
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input [31:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input [1:0] s_axi_arlock;
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input [7:0] s_axi_arlen;
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input [2:0] s_axi_arprot;
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input [3:0] s_axi_arqos;
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output s_axi_arready;
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input [2:0] s_axi_arsize;
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input s_axi_arvalid;
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//Write address channel
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input [IDW-1:0] s_axi_awid; //write address ID
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input [31:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input [1:0] s_axi_awlock;
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input [7:0] s_axi_awlen;
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input [2:0] s_axi_awprot;
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input [3:0] s_axi_awqos;
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input [2:0] s_axi_awsize;
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input s_axi_awvalid;
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output s_axi_awready;
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//Buffered write response channel
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output [IDW-1:0] s_axi_bid; //write address ID
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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//Read channel
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output [IDW-1:0] s_axi_rid; //write address ID
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output [31:0] s_axi_rdata;
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output s_axi_rlast;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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//Write channel
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input [IDW-1:0] s_axi_wid; //write address ID
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input [31:0] s_axi_wdata;
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input s_axi_wlast;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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/*****************************/
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/*MAILBOX (interrupts) */
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/*****************************/
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output embox_not_empty;
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output embox_full;
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output mailbox_not_empty;
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output mailbox_full;
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/*****************************/
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/*"Bus" Interface */
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/*****************************/
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//Master Write (from RX)
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input rxwr_clk;
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//Master Read Request (from RX)
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input rxrd_clk;
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//Slave Read Response (from RX)
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input rxrr_clk;
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//Slave Write (to TX)
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input txwr_clk;
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Slave Read Request (to TX)
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input txrd_clk;
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//Master Read Response (to TX)
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input txrr_clk;
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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/*#############################################*/
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/* END OF BLOCK INTERFACE */
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/*#############################################*/
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@ -450,454 +371,79 @@ module elink(/*AUTOARG*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [15:0] ecfg_clk_settings; // From ecfg of ecfg.v
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wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
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wire [10:0] ecfg_dataout; // From ecfg of ecfg.v
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wire [8:0] ecfg_rx_datain; // From erx of erx.v
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wire [15:0] ecfg_rx_debug; // From erx of erx.v
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wire ecfg_rx_enable; // From ecfg of ecfg.v
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wire ecfg_rx_gpio_enable; // From ecfg of ecfg.v
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wire ecfg_rx_mmu_enable; // From ecfg of ecfg.v
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wire ecfg_timeout_enable; // From ecfg of ecfg.v
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wire [3:0] ecfg_tx_ctrlmode; // From ecfg of ecfg.v
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wire [1:0] ecfg_tx_datain; // From etx of etx.v
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wire [15:0] ecfg_tx_debug; // From etx of etx.v
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wire ecfg_tx_enable; // From ecfg of ecfg.v
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wire ecfg_tx_gpio_enable; // From ecfg of ecfg.v
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wire ecfg_tx_mmu_enable; // From ecfg of ecfg.v
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wire emaxi_emrq_access; // From erx of erx.v
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wire [3:0] emaxi_emrq_ctrlmode; // From erx of erx.v
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wire [31:0] emaxi_emrq_data; // From erx of erx.v
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wire [1:0] emaxi_emrq_datamode; // From erx of erx.v
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wire [31:0] emaxi_emrq_dstaddr; // From erx of erx.v
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wire emaxi_emrq_rd_en; // From emaxi of emaxi.v
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wire [31:0] emaxi_emrq_srcaddr; // From erx of erx.v
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wire emaxi_emrq_write; // From erx of erx.v
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wire emaxi_emrr_access; // From emaxi of emaxi.v
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wire [3:0] emaxi_emrr_ctrlmode; // From emaxi of emaxi.v
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wire [31:0] emaxi_emrr_data; // From emaxi of emaxi.v
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wire [1:0] emaxi_emrr_datamode; // From emaxi of emaxi.v
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wire [31:0] emaxi_emrr_dstaddr; // From emaxi of emaxi.v
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wire emaxi_emrr_progfull; // From etx of etx.v
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wire [31:0] emaxi_emrr_srcaddr; // From emaxi of emaxi.v
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wire emaxi_emrr_write; // From emaxi of emaxi.v
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wire emaxi_emwr_access; // From erx of erx.v
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wire [3:0] emaxi_emwr_ctrlmode; // From erx of erx.v
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wire [31:0] emaxi_emwr_data; // From erx of erx.v
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wire [1:0] emaxi_emwr_datamode; // From erx of erx.v
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wire [31:0] emaxi_emwr_dstaddr; // From erx of erx.v
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wire emaxi_emwr_rd_en; // From emaxi of emaxi.v
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wire [31:0] emaxi_emwr_srcaddr; // From erx of erx.v
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wire emaxi_emwr_write; // From erx of erx.v
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wire esaxi_emrq_access; // From esaxi of esaxi.v
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wire [3:0] esaxi_emrq_ctrlmode; // From esaxi of esaxi.v
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wire [31:0] esaxi_emrq_data; // From esaxi of esaxi.v
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wire [1:0] esaxi_emrq_datamode; // From esaxi of esaxi.v
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wire [31:0] esaxi_emrq_dstaddr; // From esaxi of esaxi.v
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wire esaxi_emrq_progfull; // From etx of etx.v
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wire [31:0] esaxi_emrq_srcaddr; // From esaxi of esaxi.v
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wire esaxi_emrq_write; // From esaxi of esaxi.v
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wire esaxi_emrr_access; // From erx of erx.v
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wire [31:0] esaxi_emrr_data; // From erx of erx.v
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wire esaxi_emrr_rd_en; // From esaxi of esaxi.v
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wire esaxi_emwr_access; // From esaxi of esaxi.v
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wire [3:0] esaxi_emwr_ctrlmode; // From esaxi of esaxi.v
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wire [31:0] esaxi_emwr_data; // From esaxi of esaxi.v
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wire [1:0] esaxi_emwr_datamode; // From esaxi of esaxi.v
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wire [31:0] esaxi_emwr_dstaddr; // From esaxi of esaxi.v
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wire esaxi_emwr_progfull; // From etx of etx.v
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wire [31:0] esaxi_emwr_srcaddr; // From esaxi of esaxi.v
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wire esaxi_emwr_write; // From esaxi of esaxi.v
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wire [19:0] mi_addr; // From esaxi of esaxi.v
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wire mi_clk; // From esaxi of esaxi.v
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wire [31:0] mi_din; // From esaxi of esaxi.v
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wire [31:0] mi_ecfg_dout; // From ecfg of ecfg.v
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wire mi_ecfg_sel; // From esaxi of esaxi.v
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wire [DW-1:0] mi_embox_dout; // From embox of embox.v
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wire mi_embox_sel; // From esaxi of esaxi.v
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wire [31:0] mi_rx_emmu_dout; // From erx of erx.v
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wire mi_rx_emmu_sel; // From esaxi of esaxi.v
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wire [31:0] mi_tx_emmu_dout; // From etx of etx.v
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wire mi_tx_emmu_sel; // From esaxi of esaxi.v
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wire mi_we; // From esaxi of esaxi.v
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wire [15:0] ecfg_clk_settings; // From ecfg_base of ecfg_base.v
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wire [19:0] mi_addr; // From ecfg_if of ecfg_if.v
|
||||
wire [31:0] mi_ba_cfg_dout; // From ecfg_base of ecfg_base.v
|
||||
wire mi_clk; // From ecfg_if of ecfg_if.v
|
||||
wire [31:0] mi_din; // From ecfg_if of ecfg_if.v
|
||||
wire mi_en; // From ecfg_if of ecfg_if.v
|
||||
wire [DW-1:0] mi_rx_cfg_dout; // From erx of erx.v
|
||||
wire [DW-1:0] mi_rx_edma_dout; // From erx of erx.v
|
||||
wire [DW-1:0] mi_rx_emmu_dout; // From erx of erx.v, ...
|
||||
wire [DW-1:0] mi_rx_mailbox_dout; // From erx of erx.v
|
||||
wire [DW-1:0] mi_tx_cfg_dout; // From etx of etx.v
|
||||
wire [DW-1:0] mi_tx_emmu_dout; // From etx of etx.v
|
||||
wire mi_we; // From ecfg_if of ecfg_if.v
|
||||
wire reset; // From ereset of ereset.v
|
||||
wire soft_reset; // From ecfg of ecfg.v
|
||||
wire soft_reset; // From ecfg_base of ecfg_base.v
|
||||
wire tx_lclk; // From eclocks of eclocks.v
|
||||
wire tx_lclk90; // From eclocks of eclocks.v
|
||||
wire tx_lclk_div4; // From eclocks of eclocks.v
|
||||
// End of automatics
|
||||
|
||||
|
||||
/***********************************************************/
|
||||
/*AXI MASTER */
|
||||
/***********************************************************/
|
||||
/*emaxi AUTO_TEMPLATE (
|
||||
// Outputs
|
||||
.m00_\(.*\) (m_\1[]),
|
||||
.em\(.*\) (emaxi_em\1[]),
|
||||
);
|
||||
*/
|
||||
defparam emaxi.IDW =IDW; //ID width from instantiation
|
||||
|
||||
emaxi emaxi(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.emwr_rd_en (emaxi_emwr_rd_en), // Templated
|
||||
.emrq_rd_en (emaxi_emrq_rd_en), // Templated
|
||||
.emrr_access (emaxi_emrr_access), // Templated
|
||||
.emrr_write (emaxi_emrr_write), // Templated
|
||||
.emrr_datamode (emaxi_emrr_datamode[1:0]), // Templated
|
||||
.emrr_ctrlmode (emaxi_emrr_ctrlmode[3:0]), // Templated
|
||||
.emrr_dstaddr (emaxi_emrr_dstaddr[31:0]), // Templated
|
||||
.emrr_data (emaxi_emrr_data[31:0]), // Templated
|
||||
.emrr_srcaddr (emaxi_emrr_srcaddr[31:0]), // Templated
|
||||
.m_axi_awid (m_axi_awid[IDW-1:0]),
|
||||
.m_axi_awaddr (m_axi_awaddr[31:0]),
|
||||
.m_axi_awlen (m_axi_awlen[7:0]),
|
||||
.m_axi_awsize (m_axi_awsize[2:0]),
|
||||
.m_axi_awburst (m_axi_awburst[1:0]),
|
||||
.m_axi_awlock (m_axi_awlock[1:0]),
|
||||
.m_axi_awcache (m_axi_awcache[3:0]),
|
||||
.m_axi_awprot (m_axi_awprot[2:0]),
|
||||
.m_axi_awqos (m_axi_awqos[3:0]),
|
||||
.m_axi_awvalid (m_axi_awvalid),
|
||||
.m_axi_wid (m_axi_wid[IDW-1:0]),
|
||||
.m_axi_wdata (m_axi_wdata[63:0]),
|
||||
.m_axi_wstrb (m_axi_wstrb[7:0]),
|
||||
.m_axi_wlast (m_axi_wlast),
|
||||
.m_axi_wvalid (m_axi_wvalid),
|
||||
.m_axi_bready (m_axi_bready),
|
||||
.m_axi_arid (m_axi_arid[IDW-1:0]),
|
||||
.m_axi_araddr (m_axi_araddr[31:0]),
|
||||
.m_axi_arlen (m_axi_arlen[7:0]),
|
||||
.m_axi_arsize (m_axi_arsize[2:0]),
|
||||
.m_axi_arburst (m_axi_arburst[1:0]),
|
||||
.m_axi_arlock (m_axi_arlock[1:0]),
|
||||
.m_axi_arcache (m_axi_arcache[3:0]),
|
||||
.m_axi_arprot (m_axi_arprot[2:0]),
|
||||
.m_axi_arqos (m_axi_arqos[3:0]),
|
||||
.m_axi_arvalid (m_axi_arvalid),
|
||||
.m_axi_rready (m_axi_rready),
|
||||
// Inputs
|
||||
.emwr_access (emaxi_emwr_access), // Templated
|
||||
.emwr_write (emaxi_emwr_write), // Templated
|
||||
.emwr_datamode (emaxi_emwr_datamode[1:0]), // Templated
|
||||
.emwr_ctrlmode (emaxi_emwr_ctrlmode[3:0]), // Templated
|
||||
.emwr_dstaddr (emaxi_emwr_dstaddr[31:0]), // Templated
|
||||
.emwr_data (emaxi_emwr_data[31:0]), // Templated
|
||||
.emwr_srcaddr (emaxi_emwr_srcaddr[31:0]), // Templated
|
||||
.emrq_access (emaxi_emrq_access), // Templated
|
||||
.emrq_write (emaxi_emrq_write), // Templated
|
||||
.emrq_datamode (emaxi_emrq_datamode[1:0]), // Templated
|
||||
.emrq_ctrlmode (emaxi_emrq_ctrlmode[3:0]), // Templated
|
||||
.emrq_dstaddr (emaxi_emrq_dstaddr[31:0]), // Templated
|
||||
.emrq_data (emaxi_emrq_data[31:0]), // Templated
|
||||
.emrq_srcaddr (emaxi_emrq_srcaddr[31:0]), // Templated
|
||||
.emrr_progfull (emaxi_emrr_progfull), // Templated
|
||||
.m_axi_aclk (m_axi_aclk),
|
||||
.m_axi_aresetn (m_axi_aresetn),
|
||||
.m_axi_awready (m_axi_awready),
|
||||
.m_axi_wready (m_axi_wready),
|
||||
.m_axi_bid (m_axi_bid[IDW-1:0]),
|
||||
.m_axi_bresp (m_axi_bresp[1:0]),
|
||||
.m_axi_bvalid (m_axi_bvalid),
|
||||
.m_axi_arready (m_axi_arready),
|
||||
.m_axi_rid (m_axi_rid[IDW-1:0]),
|
||||
.m_axi_rdata (m_axi_rdata[63:0]),
|
||||
.m_axi_rresp (m_axi_rresp[1:0]),
|
||||
.m_axi_rlast (m_axi_rlast),
|
||||
.m_axi_rvalid (m_axi_rvalid));
|
||||
|
||||
/***********************************************************/
|
||||
/*AXI SLAVE */
|
||||
/*ELINK CONFIGURATION INTERFACE */
|
||||
/***********************************************************/
|
||||
/*esaxi AUTO_TEMPLATE (
|
||||
// Outputs
|
||||
.s00_\(.*\) (s_\1[]),
|
||||
.emwr_\(.*\) (esaxi_emwr_\1[]),
|
||||
.emrq_\(.*\) (esaxi_emrq_\1[]),
|
||||
.emrr_\(.*\) (esaxi_emrr_\1[]),
|
||||
);
|
||||
*/
|
||||
|
||||
defparam esaxi.ELINKID=ELINKID; //passing along ID from top level
|
||||
defparam esaxi.IDW =IDW; //ID width from instantiation
|
||||
ecfg_if ecfg_if(.rxrr_access (),//TODO: readback, mux with rr
|
||||
.rxrr_packet (),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_clk (mi_clk),
|
||||
.mi_en (mi_en),
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[19:0]),
|
||||
.mi_din (mi_din[31:0]),
|
||||
// Inputs
|
||||
.txwr_clk (txwr_clk),
|
||||
.txwr_access (txwr_access),
|
||||
.txwr_packet (txwr_packet[PW-1:0]),
|
||||
.txrd_access (txrd_access),
|
||||
.txrd_packet (txrd_packet[PW-1:0]),
|
||||
.rxrr_clk (rxrr_clk),
|
||||
.mi_ba_cfg_dout (mi_ba_cfg_dout[31:0]),
|
||||
.mi_rx_cfg_dout (mi_rx_cfg_dout[DW-1:0]),
|
||||
.mi_rx_edma_dout (mi_rx_edma_dout[DW-1:0]),
|
||||
.mi_rx_emmu_dout (mi_rx_emmu_dout[DW-1:0]),
|
||||
.mi_rx_mailbox_dout (mi_rx_mailbox_dout[DW-1:0]),
|
||||
.mi_tx_cfg_dout (mi_tx_cfg_dout[DW-1:0]),
|
||||
.mi_tx_emmu_dout (mi_tx_emmu_dout[DW-1:0]));
|
||||
|
||||
esaxi esaxi(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.emwr_access (esaxi_emwr_access), // Templated
|
||||
.emwr_write (esaxi_emwr_write), // Templated
|
||||
.emwr_datamode (esaxi_emwr_datamode[1:0]), // Templated
|
||||
.emwr_ctrlmode (esaxi_emwr_ctrlmode[3:0]), // Templated
|
||||
.emwr_dstaddr (esaxi_emwr_dstaddr[31:0]), // Templated
|
||||
.emwr_data (esaxi_emwr_data[31:0]), // Templated
|
||||
.emwr_srcaddr (esaxi_emwr_srcaddr[31:0]), // Templated
|
||||
.emrq_access (esaxi_emrq_access), // Templated
|
||||
.emrq_write (esaxi_emrq_write), // Templated
|
||||
.emrq_datamode (esaxi_emrq_datamode[1:0]), // Templated
|
||||
.emrq_ctrlmode (esaxi_emrq_ctrlmode[3:0]), // Templated
|
||||
.emrq_dstaddr (esaxi_emrq_dstaddr[31:0]), // Templated
|
||||
.emrq_data (esaxi_emrq_data[31:0]), // Templated
|
||||
.emrq_srcaddr (esaxi_emrq_srcaddr[31:0]), // Templated
|
||||
.emrr_rd_en (esaxi_emrr_rd_en), // Templated
|
||||
.mi_clk (mi_clk),
|
||||
.mi_rx_emmu_sel (mi_rx_emmu_sel),
|
||||
.mi_tx_emmu_sel (mi_tx_emmu_sel),
|
||||
.mi_ecfg_sel (mi_ecfg_sel),
|
||||
.mi_embox_sel (mi_embox_sel),
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[19:0]),
|
||||
.mi_din (mi_din[31:0]),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_bid (s_axi_bid[IDW-1:0]),
|
||||
.s_axi_bresp (s_axi_bresp[1:0]),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_rid (s_axi_rid[IDW-1:0]),
|
||||
.s_axi_rdata (s_axi_rdata[31:0]),
|
||||
.s_axi_rlast (s_axi_rlast),
|
||||
.s_axi_rresp (s_axi_rresp[1:0]),
|
||||
.s_axi_rvalid (s_axi_rvalid),
|
||||
.s_axi_wready (s_axi_wready),
|
||||
// Inputs
|
||||
.emwr_progfull (esaxi_emwr_progfull), // Templated
|
||||
.emrq_progfull (esaxi_emrq_progfull), // Templated
|
||||
.emrr_data (esaxi_emrr_data[31:0]), // Templated
|
||||
.emrr_access (esaxi_emrr_access), // Templated
|
||||
.mi_ecfg_dout (mi_ecfg_dout[31:0]),
|
||||
.mi_tx_emmu_dout (mi_tx_emmu_dout[31:0]),
|
||||
.mi_rx_emmu_dout (mi_rx_emmu_dout[31:0]),
|
||||
.mi_embox_dout (mi_embox_dout[31:0]),
|
||||
.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
|
||||
.ecfg_coreid (ecfg_coreid[11:0]),
|
||||
.ecfg_timeout_enable (ecfg_timeout_enable),
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_arid (s_axi_arid[IDW-1:0]),
|
||||
.s_axi_araddr (s_axi_araddr[31:0]),
|
||||
.s_axi_arburst (s_axi_arburst[1:0]),
|
||||
.s_axi_arcache (s_axi_arcache[3:0]),
|
||||
.s_axi_arlock (s_axi_arlock[1:0]),
|
||||
.s_axi_arlen (s_axi_arlen[7:0]),
|
||||
.s_axi_arprot (s_axi_arprot[2:0]),
|
||||
.s_axi_arqos (s_axi_arqos[3:0]),
|
||||
.s_axi_arsize (s_axi_arsize[2:0]),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_awid (s_axi_awid[IDW-1:0]),
|
||||
.s_axi_awaddr (s_axi_awaddr[31:0]),
|
||||
.s_axi_awburst (s_axi_awburst[1:0]),
|
||||
.s_axi_awcache (s_axi_awcache[3:0]),
|
||||
.s_axi_awlock (s_axi_awlock[1:0]),
|
||||
.s_axi_awlen (s_axi_awlen[7:0]),
|
||||
.s_axi_awprot (s_axi_awprot[2:0]),
|
||||
.s_axi_awqos (s_axi_awqos[3:0]),
|
||||
.s_axi_awsize (s_axi_awsize[2:0]),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.s_axi_wid (s_axi_wid[IDW-1:0]),
|
||||
.s_axi_wdata (s_axi_wdata[31:0]),
|
||||
.s_axi_wlast (s_axi_wlast),
|
||||
.s_axi_wstrb (s_axi_wstrb[3:0]),
|
||||
.s_axi_wvalid (s_axi_wvalid));
|
||||
|
||||
/***********************************************************/
|
||||
/*RECEIVER */
|
||||
/***********************************************************/
|
||||
/*erx AUTO_TEMPLATE (
|
||||
.mi_dout (mi_rx_emmu_dout[]),
|
||||
.mi_en (mi_rx_emmu_sel),
|
||||
.emwr_\(.*\) (emaxi_emwr_\1[]),
|
||||
.emrq_\(.*\) (emaxi_emrq_\1[]),
|
||||
.emrr_\(.*\) (esaxi_emrr_\1[]),
|
||||
);
|
||||
*/
|
||||
|
||||
|
||||
erx erx(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.ecfg_rx_debug (ecfg_rx_debug[15:0]),
|
||||
.ecfg_rx_datain (ecfg_rx_datain[8:0]),
|
||||
.mi_dout (mi_rx_emmu_dout[31:0]), // Templated
|
||||
.emwr_access (emaxi_emwr_access), // Templated
|
||||
.emwr_write (emaxi_emwr_write), // Templated
|
||||
.emwr_datamode (emaxi_emwr_datamode[1:0]), // Templated
|
||||
.emwr_ctrlmode (emaxi_emwr_ctrlmode[3:0]), // Templated
|
||||
.emwr_dstaddr (emaxi_emwr_dstaddr[31:0]), // Templated
|
||||
.emwr_data (emaxi_emwr_data[31:0]), // Templated
|
||||
.emwr_srcaddr (emaxi_emwr_srcaddr[31:0]), // Templated
|
||||
.emrq_access (emaxi_emrq_access), // Templated
|
||||
.emrq_write (emaxi_emrq_write), // Templated
|
||||
.emrq_datamode (emaxi_emrq_datamode[1:0]), // Templated
|
||||
.emrq_ctrlmode (emaxi_emrq_ctrlmode[3:0]), // Templated
|
||||
.emrq_dstaddr (emaxi_emrq_dstaddr[31:0]), // Templated
|
||||
.emrq_data (emaxi_emrq_data[31:0]), // Templated
|
||||
.emrq_srcaddr (emaxi_emrq_srcaddr[31:0]), // Templated
|
||||
.emrr_access (esaxi_emrr_access), // Templated
|
||||
.emrr_data (esaxi_emrr_data[31:0]), // Templated
|
||||
.rxo_wr_wait_p (rxo_wr_wait_p),
|
||||
.rxo_wr_wait_n (rxo_wr_wait_n),
|
||||
.rxo_rd_wait_p (rxo_rd_wait_p),
|
||||
.rxo_rd_wait_n (rxo_rd_wait_n),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.m_axi_aclk (m_axi_aclk),
|
||||
.ecfg_rx_enable (ecfg_rx_enable),
|
||||
.ecfg_rx_mmu_enable (ecfg_rx_mmu_enable),
|
||||
.ecfg_rx_gpio_enable (ecfg_rx_gpio_enable),
|
||||
.ecfg_dataout (ecfg_dataout[1:0]),
|
||||
.mi_clk (mi_clk),
|
||||
.mi_en (mi_rx_emmu_sel), // Templated
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[15:0]),
|
||||
.mi_din (mi_din[31:0]),
|
||||
.emwr_rd_en (emaxi_emwr_rd_en), // Templated
|
||||
.emrq_rd_en (emaxi_emrq_rd_en), // Templated
|
||||
.emrr_rd_en (esaxi_emrr_rd_en), // Templated
|
||||
.rxi_lclk_p (rxi_lclk_p),
|
||||
.rxi_lclk_n (rxi_lclk_n),
|
||||
.rxi_frame_p (rxi_frame_p),
|
||||
.rxi_frame_n (rxi_frame_n),
|
||||
.rxi_data_p (rxi_data_p[7:0]),
|
||||
.rxi_data_n (rxi_data_n[7:0]));
|
||||
|
||||
/***********************************************************/
|
||||
/*TRANSMITTER */
|
||||
/***********************************************************/
|
||||
/*etx AUTO_TEMPLATE (
|
||||
.mi_dout (mi_tx_emmu_dout[]),
|
||||
.mi_en (mi_tx_emmu_sel),
|
||||
.emwr_\(.*\) (esaxi_emwr_\1[]),
|
||||
.emrq_\(.*\) (esaxi_emrq_\1[]),
|
||||
.emrr_\(.*\) (emaxi_emrr_\1[]),
|
||||
);
|
||||
*/
|
||||
|
||||
etx etx(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.ecfg_tx_datain (ecfg_tx_datain[1:0]),
|
||||
.ecfg_tx_debug (ecfg_tx_debug[15:0]),
|
||||
.emrq_progfull (esaxi_emrq_progfull), // Templated
|
||||
.emwr_progfull (esaxi_emwr_progfull), // Templated
|
||||
.emrr_progfull (emaxi_emrr_progfull), // Templated
|
||||
.txo_lclk_p (txo_lclk_p),
|
||||
.txo_lclk_n (txo_lclk_n),
|
||||
.txo_frame_p (txo_frame_p),
|
||||
.txo_frame_n (txo_frame_n),
|
||||
.txo_data_p (txo_data_p[7:0]),
|
||||
.txo_data_n (txo_data_n[7:0]),
|
||||
.mi_dout (mi_tx_emmu_dout[31:0]), // Templated
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.tx_lclk (tx_lclk),
|
||||
.tx_lclk90 (tx_lclk90),
|
||||
.tx_lclk_div4 (tx_lclk_div4),
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.m_axi_aclk (m_axi_aclk),
|
||||
.ecfg_tx_enable (ecfg_tx_enable),
|
||||
.ecfg_tx_gpio_enable (ecfg_tx_gpio_enable),
|
||||
.ecfg_tx_mmu_enable (ecfg_tx_mmu_enable),
|
||||
.ecfg_dataout (ecfg_dataout[8:0]),
|
||||
.emrq_access (esaxi_emrq_access), // Templated
|
||||
.emrq_write (esaxi_emrq_write), // Templated
|
||||
.emrq_datamode (esaxi_emrq_datamode[1:0]), // Templated
|
||||
.emrq_ctrlmode (esaxi_emrq_ctrlmode[3:0]), // Templated
|
||||
.emrq_dstaddr (esaxi_emrq_dstaddr[31:0]), // Templated
|
||||
.emrq_data (esaxi_emrq_data[31:0]), // Templated
|
||||
.emrq_srcaddr (esaxi_emrq_srcaddr[31:0]), // Templated
|
||||
.emwr_access (esaxi_emwr_access), // Templated
|
||||
.emwr_write (esaxi_emwr_write), // Templated
|
||||
.emwr_datamode (esaxi_emwr_datamode[1:0]), // Templated
|
||||
.emwr_ctrlmode (esaxi_emwr_ctrlmode[3:0]), // Templated
|
||||
.emwr_dstaddr (esaxi_emwr_dstaddr[31:0]), // Templated
|
||||
.emwr_data (esaxi_emwr_data[31:0]), // Templated
|
||||
.emwr_srcaddr (esaxi_emwr_srcaddr[31:0]), // Templated
|
||||
.emrr_access (emaxi_emrr_access), // Templated
|
||||
.emrr_write (emaxi_emrr_write), // Templated
|
||||
.emrr_datamode (emaxi_emrr_datamode[1:0]), // Templated
|
||||
.emrr_ctrlmode (emaxi_emrr_ctrlmode[3:0]), // Templated
|
||||
.emrr_dstaddr (emaxi_emrr_dstaddr[31:0]), // Templated
|
||||
.emrr_data (emaxi_emrr_data[31:0]), // Templated
|
||||
.emrr_srcaddr (emaxi_emrr_srcaddr[31:0]), // Templated
|
||||
.txi_wr_wait_p (txi_wr_wait_p),
|
||||
.txi_wr_wait_n (txi_wr_wait_n),
|
||||
.txi_rd_wait_p (txi_rd_wait_p),
|
||||
.txi_rd_wait_n (txi_rd_wait_n),
|
||||
.mi_clk (mi_clk),
|
||||
.mi_en (mi_tx_emmu_sel), // Templated
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[15:0]),
|
||||
.mi_din (mi_din[31:0]));
|
||||
|
||||
/***********************************************************/
|
||||
/*ELINK CONFIGURATION REGISTERES */
|
||||
/***********************************************************/
|
||||
|
||||
/*ecfg AUTO_TEMPLATE (
|
||||
.mi_dout (mi_ecfg_dout[]),
|
||||
.mi_en (mi_ecfg_sel),
|
||||
/*ecfg_base AUTO_TEMPLATE (
|
||||
.mi_dout (mi_ba_cfg_dout[]),
|
||||
.ecfg_reset (reset),
|
||||
.clk (mi_clk),
|
||||
);
|
||||
)
|
||||
*/
|
||||
|
||||
|
||||
ecfg ecfg(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.soft_reset (soft_reset),
|
||||
.mi_dout (mi_ecfg_dout[31:0]), // Templated
|
||||
.ecfg_tx_enable (ecfg_tx_enable),
|
||||
.ecfg_tx_mmu_enable (ecfg_tx_mmu_enable),
|
||||
.ecfg_tx_gpio_enable (ecfg_tx_gpio_enable),
|
||||
.ecfg_tx_ctrlmode (ecfg_tx_ctrlmode[3:0]),
|
||||
.ecfg_timeout_enable (ecfg_timeout_enable),
|
||||
.ecfg_rx_enable (ecfg_rx_enable),
|
||||
.ecfg_rx_mmu_enable (ecfg_rx_mmu_enable),
|
||||
.ecfg_rx_gpio_enable (ecfg_rx_gpio_enable),
|
||||
.ecfg_clk_settings (ecfg_clk_settings[15:0]),
|
||||
.ecfg_coreid (ecfg_coreid[11:0]),
|
||||
.ecfg_dataout (ecfg_dataout[10:0]),
|
||||
// Inputs
|
||||
.hard_reset (hard_reset),
|
||||
.mi_clk (mi_clk),
|
||||
.mi_en (mi_ecfg_sel), // Templated
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[19:0]),
|
||||
.mi_din (mi_din[31:0]),
|
||||
.ecfg_rx_datain (ecfg_rx_datain[8:0]),
|
||||
.ecfg_tx_datain (ecfg_tx_datain[1:0]),
|
||||
.embox_not_empty (embox_not_empty),
|
||||
.embox_full (embox_full),
|
||||
.ecfg_tx_debug (ecfg_tx_debug[15:0]),
|
||||
.ecfg_rx_debug (ecfg_rx_debug[15:0]));
|
||||
|
||||
|
||||
/***********************************************************/
|
||||
/*GENERAL PURPOSE MAILBOX */
|
||||
/***********************************************************/
|
||||
/*embox AUTO_TEMPLATE (
|
||||
.mi_dout (mi_embox_dout[]),
|
||||
.mi_en (mi_embox_sel),
|
||||
);
|
||||
*/
|
||||
|
||||
embox embox(.clk (s_axi_aclk),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_dout (mi_embox_dout[DW-1:0]), // Templated
|
||||
.embox_full (embox_full),
|
||||
.embox_not_empty (embox_not_empty),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.mi_en (mi_embox_sel), // Templated
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[19:0]),
|
||||
.mi_din (mi_din[DW-1:0]));
|
||||
ecfg_base ecfg_base(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.soft_reset (soft_reset),
|
||||
.mi_dout (mi_ba_cfg_dout[31:0]), // Templated
|
||||
.ecfg_clk_settings(ecfg_clk_settings[15:0]),
|
||||
.colid (colid[3:0]),
|
||||
.rowid (rowid[3:0]),
|
||||
// Inputs
|
||||
.hard_reset (hard_reset),
|
||||
.mi_clk (mi_clk),
|
||||
.mi_en (mi_en),
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[19:0]),
|
||||
.mi_din (mi_din[31:0]));
|
||||
|
||||
/***********************************************************/
|
||||
/*RESET CIRCUITRY */
|
||||
@ -926,10 +472,114 @@ module elink(/*AUTOARG*/
|
||||
.hard_reset (hard_reset),
|
||||
.ecfg_clk_settings (ecfg_clk_settings[15:0]),
|
||||
.clkbypass (clkbypass[2:0]));
|
||||
|
||||
|
||||
|
||||
/***********************************************************/
|
||||
/*RECEIVER */
|
||||
/***********************************************************/
|
||||
/*erx AUTO_TEMPLATE (
|
||||
.mi_dout (mi_rx_emmu_dout[]),
|
||||
.emwr_\(.*\) (emaxi_emwr_\1[]),
|
||||
.emrq_\(.*\) (emaxi_emrq_\1[]),
|
||||
.emrr_\(.*\) (esaxi_emrr_\1[]),
|
||||
);
|
||||
*/
|
||||
|
||||
|
||||
erx erx(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.rxo_wr_wait_p (rxo_wr_wait_p),
|
||||
.rxo_wr_wait_n (rxo_wr_wait_n),
|
||||
.rxo_rd_wait_p (rxo_rd_wait_p),
|
||||
.rxo_rd_wait_n (rxo_rd_wait_n),
|
||||
.rxwr_access (rxwr_access),
|
||||
.rxwr_packet (rxwr_packet[PW-1:0]),
|
||||
.rxrd_access (rxrd_access),
|
||||
.rxrd_packet (rxrd_packet[PW-1:0]),
|
||||
.rxrr_access (rxrr_access),
|
||||
.rxrr_packet (rxrr_packet[PW-1:0]),
|
||||
.mi_dout (mi_rx_emmu_dout[31:0]), // Templated
|
||||
.mi_rx_edma_dout (mi_rx_edma_dout[DW-1:0]),
|
||||
.mi_rx_emmu_dout (mi_rx_emmu_dout[DW-1:0]),
|
||||
.mi_rx_cfg_dout (mi_rx_cfg_dout[DW-1:0]),
|
||||
.mi_rx_mailbox_dout (mi_rx_mailbox_dout[DW-1:0]),
|
||||
.mailbox_full (mailbox_full),
|
||||
.mailbox_not_empty (mailbox_not_empty),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.rxi_lclk_p (rxi_lclk_p),
|
||||
.rxi_lclk_n (rxi_lclk_n),
|
||||
.rxi_frame_p (rxi_frame_p),
|
||||
.rxi_frame_n (rxi_frame_n),
|
||||
.rxi_data_p (rxi_data_p[7:0]),
|
||||
.rxi_data_n (rxi_data_n[7:0]),
|
||||
.rxwr_clk (rxwr_clk),
|
||||
.rxwr_wait (rxwr_wait),
|
||||
.rxrd_clk (rxrd_clk),
|
||||
.rxrd_wait (rxrd_wait),
|
||||
.rxrr_clk (rxrr_clk),
|
||||
.rxrr_wait (rxrr_wait),
|
||||
.mi_clk (mi_clk),
|
||||
.mi_en (mi_en),
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[19:0]),
|
||||
.mi_din (mi_din[31:0]));
|
||||
|
||||
/***********************************************************/
|
||||
/*TRANSMITTER */
|
||||
/***********************************************************/
|
||||
/*etx AUTO_TEMPLATE (
|
||||
.emwr_\(.*\) (esaxi_emwr_\1[]),
|
||||
.emrq_\(.*\) (esaxi_emrq_\1[]),
|
||||
.emrr_\(.*\) (emaxi_emrr_\1[]),
|
||||
);
|
||||
*/
|
||||
|
||||
etx etx(
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_tx_emmu_dout (mi_tx_emmu_dout[DW-1:0]),
|
||||
.mi_tx_cfg_dout (mi_tx_cfg_dout[DW-1:0]),
|
||||
.txrd_wait (txrd_wait),
|
||||
.txwr_wait (txwr_wait),
|
||||
.txrr_wait (txrr_wait),
|
||||
.txo_lclk_p (txo_lclk_p),
|
||||
.txo_lclk_n (txo_lclk_n),
|
||||
.txo_frame_p (txo_frame_p),
|
||||
.txo_frame_n (txo_frame_n),
|
||||
.txo_data_p (txo_data_p[7:0]),
|
||||
.txo_data_n (txo_data_n[7:0]),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.tx_lclk (tx_lclk),
|
||||
.tx_lclk90 (tx_lclk90),
|
||||
.tx_lclk_div4 (tx_lclk_div4),
|
||||
.mi_clk (mi_clk),
|
||||
.mi_en (mi_en),
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[19:0]),
|
||||
.mi_din (mi_din[31:0]),
|
||||
.txrd_clk (txrd_clk),
|
||||
.txrd_access (txrd_access),
|
||||
.txrd_packet (txrd_packet[PW-1:0]),
|
||||
.txwr_clk (txwr_clk),
|
||||
.txwr_access (txwr_access),
|
||||
.txwr_packet (txwr_packet[PW-1:0]),
|
||||
.txrr_clk (txrr_clk),
|
||||
.txrr_access (txrr_access),
|
||||
.txrr_packet (txrr_packet[PW-1:0]),
|
||||
.txi_wr_wait_p (txi_wr_wait_p),
|
||||
.txi_wr_wait_n (txi_wr_wait_n),
|
||||
.txi_rd_wait_p (txi_rd_wait_p),
|
||||
.txi_rd_wait_n (txi_rd_wait_n));
|
||||
|
||||
|
||||
|
||||
endmodule // elink
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../../embox/hdl" "../../erx/hdl" "../../etx/hdl" "../../axi/hdl" "../../ecfg/hdl" "../../eclock/hdl")
|
||||
// verilog-library-directories:("." "../../emailbox/hdl" "../../erx/hdl" "../../etx/hdl" "../../axi/hdl" "../../ecfg/hdl" "../../eclock/hdl")
|
||||
// End:
|
||||
|
||||
/*
|
||||
|
Loading…
x
Reference in New Issue
Block a user